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    Semiconductor device with tunable epitaxy structures and method of forming the same
    3.
    发明授权
    Semiconductor device with tunable epitaxy structures and method of forming the same 有权

    公开(公告)号：US11581226B2

    公开(公告)日：2023-02-14

    申请号：US16938340

    申请日：2020-07-24

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Shih-Hao Lin ,  Tzu-Hsiang Hsu ,  Chong-De Lien ,  Szu-Chi Yang ,  Hsin-Wen Su ,  Chih-Hsiang Huang

    IPC: H01L21/8238 ,  H01L21/306 ,  H01L27/11 ,  H01L27/092

    Abstract: Semiconductor device and the manufacturing method thereof are disclosed herein. An exemplary method comprises forming first and second semiconductor fins in first and second regions of a substrate, respectively; forming first and second dummy gate stacks over the first and second semiconductor fins, respectively, and forming a spacer layer over the first and the second dummy gate stacks; forming a first pattern layer with a thickness along the spacer layer in the first region; form a first source/drain (S/D) trench along the first pattern layer and epitaxially growing a first epitaxial feature therein; removing the first pattern layer to expose the spacer layer; forming a second pattern layer with a different thickness along the spacer layer in the second region; form a second S/D trench along the second pattern layer and epitaxially growing a second epitaxial feature therein; and removing the second pattern layer to expose the spacer layer.

    Semiconductor Device With Tunable Epitaxy Structures And Method Of Forming The Same
    4.
    发明申请
    Semiconductor Device With Tunable Epitaxy Structures And Method Of Forming The Same 有权

    公开(公告)号：US20210098311A1

    公开(公告)日：2021-04-01

    申请号：US16938340

    申请日：2020-07-24

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Shih-Hao Lin ,  Tzu-Hsiang Hsu ,  Chong-De Lien ,  Szu-Chi Yang ,  Hsin-Wen Su ,  Chih-Hsiang Huang

    IPC: H01L21/8238 ,  H01L27/11 ,  H01L21/306

    Abstract: Semiconductor device and the manufacturing method thereof are disclosed herein. An exemplary method comprises forming first and second semiconductor fins in first and second regions of a substrate, respectively; forming first and second dummy gate stacks over the first and second semiconductor fins, respectively, and forming a spacer layer over the first and the second dummy gate stacks; forming a first pattern layer with a thickness along the spacer layer in the first region; form a first source/drain (S/D) trench along the first pattern layer and epitaxially growing a first epitaxial feature therein; removing the first pattern layer to expose the spacer layer; forming a second pattern layer with a different thickness along the spacer layer in the second region; form a second S/D trench along the second pattern layer and epitaxially growing a second epitaxial feature therein; and removing the second pattern layer to expose the spacer layer.

    Semiconductor Device With Tunable Epitaxy Structures And Method Of Forming The Same
    5.
    发明申请
    Semiconductor Device With Tunable Epitaxy Structures And Method Of Forming The Same 有权

    公开(公告)号：US20220359308A1

    公开(公告)日：2022-11-10

    申请号：US17815085

    申请日：2022-07-26

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Shih-Hao Lin ,  Tzu-Hsiang Hsu ,  Chong-De Lien ,  Szu-Chi Yang ,  Hsin-Wen Su ,  Chih-Hsiang Huang

    IPC: H01L21/8238 ,  H01L21/306 ,  H01L27/11

    Abstract: Semiconductor device and the manufacturing method thereof are disclosed herein. An exemplary method comprises forming first and second semiconductor fins in first and second regions of a substrate, respectively; forming first and second dummy gate stacks over the first and second semiconductor fins, respectively, and forming a spacer layer over the first and the second dummy gate stacks; forming a first pattern layer with a thickness along the spacer layer in the first region; form a first source/drain (S/D) trench along the first pattern layer and epitaxially growing a first epitaxial feature therein; removing the first pattern layer to expose the spacer layer; forming a second pattern layer with a different thickness along the spacer layer in the second region; form a second S/D trench along the second pattern layer and epitaxially growing a second epitaxial feature therein; and removing the second pattern layer to expose the spacer layer.

    Static random access memory and manufacturing method thereof
    8.
    发明授权
    Static random access memory and manufacturing method thereof 有权

    公开(公告)号：US10032782B2

    公开(公告)日：2018-07-24

    申请号：US15059021

    申请日：2016-03-02

    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

    Inventor： Kuo-Hsiu Hsu ,  Chong-De Lien

    IPC: H01L27/088 ,  H01L27/11 ,  H01L27/105 ,  H01L29/66 ,  H01L29/06 ,  H01L29/78 ,  H01L27/02 ,  H01L29/423

    Abstract: A static random access memory (SRAM) cell includes first through fourth transistors being first type transistors and fifth and sixth transistors being second type transistors. Source regions of the first and second transistors are formed by a first source diffusion region, source regions of the fifth and sixth transistors are formed by second and third source diffusion regions, respectively, and source regions of the third and fourth transistors are formed by a fourth source diffusion region. The SRAM cell further includes a first data storage electrode linearly extending from a first gate line of the third and sixth transistors and electrically connecting the first gate line and the first and second source diffusion regions, and a second data storage electrode linearly extending from a second gate line of the second and fifth transistors and electrically connecting the second gate line and the third and fourth source diffusion regions.

    Static random access memory and manufacturing method thereof
    9.
    发明授权
    Static random access memory and manufacturing method thereof 有权

    公开(公告)号：US10515970B2

    公开(公告)日：2019-12-24

    申请号：US16042304

    申请日：2018-07-23

    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

    Inventor： Kuo-Hsiu Hsu ,  Chong-De Lien

    IPC: H01L27/11 ,  H01L29/06 ,  H01L27/02 ,  H01L27/105 ,  H01L29/66 ,  H01L29/78 ,  H01L29/423

    Abstract: A static random access memory (SRAM) cell includes first through fourth transistors being first type transistors and fifth and sixth transistors being second type transistors. Source regions of the first and second transistors are formed by a first source diffusion region, source regions of the fifth and sixth transistors are formed by second and third source diffusion regions, respectively, and source regions of the third and fourth transistors are formed by a fourth source diffusion region. The SRAM cell further includes a first data storage electrode linearly extending from a first gate line of the third and sixth transistors and electrically connecting the first gate line and the first and second source diffusion regions, and a second data storage electrode linearly extending from a second gate line of the second and fifth transistors and electrically connecting the second gate line and the third and fourth source diffusion regions.

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