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    Method of making lower parasitic capacitance FinFET
    1.
    发明授权
    Method of making lower parasitic capacitance FinFET 有权
    制造较低寄生电容FinFET的方法

    公开(公告)号：US08697539B2

    公开(公告)日：2014-04-15

    申请号：US13719460

    申请日：2012-12-19

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Chih-Hsiang Huang ,  Chia-Pin Lin

    IPC: H01L29/76

    CPC classification number: H01L21/76224 ,  H01L21/823431 ,  H01L29/66795 ,  H01L29/7843 ,  H01L29/7853

    Abstract: An integrated circuit device includes a gate region extending above a semiconductor substrate and extending in a first longitudinal direction. A first fin has a first sidewall that extends in a second longitudinal direction above the semiconductor substrate such that the first fin intersects the gate region. A second fin has a second sidewall extending in the second direction above the semiconductor substrate such that the second fin intersects the gate region. A shallow trench isolation (STI) region is formed in the semiconductor substrate between the first and second sidewalls of the first and second fins. A conductive layer disposed over the first insulating layer and over top surfaces of the first and second fins. A first insulating layer is disposed between an upper surface of the STI region and a lower surface of the conductive layer to separate the STI region from the conductive layer.

    Abstract translation: 集成电路器件包括在半导体衬底上延伸并在第一纵向方向上延伸的栅极区域。 第一翅片具有第一侧壁，其在半导体衬底上方的第二纵向方向上延伸，使得第一鳍片与栅极区域相交。 第二鳍片具有在半导体衬底上方的第二方向上延伸的第二侧壁，使得第二鳍片与栅极区域相交。 在第一和第二鳍片的第一和第二侧壁之间的半导体衬底中形成浅沟槽隔离（STI）区域。 布置在所述第一绝缘层之上和所述第一和第二鳍片的顶表面之上的导电层。 第一绝缘层设置在STI区的上表面和导电层的下表面之间，以将STI区与导电层分离。

    Semiconductor Device With Tunable Epitaxy Structures And Method Of Forming The Same
    2.
    发明申请
    Semiconductor Device With Tunable Epitaxy Structures And Method Of Forming The Same 有权

    公开(公告)号：US20220359308A1

    公开(公告)日：2022-11-10

    申请号：US17815085

    申请日：2022-07-26

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Shih-Hao Lin ,  Tzu-Hsiang Hsu ,  Chong-De Lien ,  Szu-Chi Yang ,  Hsin-Wen Su ,  Chih-Hsiang Huang

    IPC: H01L21/8238 ,  H01L21/306 ,  H01L27/11

    Abstract: Semiconductor device and the manufacturing method thereof are disclosed herein. An exemplary method comprises forming first and second semiconductor fins in first and second regions of a substrate, respectively; forming first and second dummy gate stacks over the first and second semiconductor fins, respectively, and forming a spacer layer over the first and the second dummy gate stacks; forming a first pattern layer with a thickness along the spacer layer in the first region; form a first source/drain (S/D) trench along the first pattern layer and epitaxially growing a first epitaxial feature therein; removing the first pattern layer to expose the spacer layer; forming a second pattern layer with a different thickness along the spacer layer in the second region; form a second S/D trench along the second pattern layer and epitaxially growing a second epitaxial feature therein; and removing the second pattern layer to expose the spacer layer.

    Semiconductor device with tunable epitaxy structures and method of forming the same
    6.
    发明授权
    Semiconductor device with tunable epitaxy structures and method of forming the same 有权

    公开(公告)号：US11581226B2

    公开(公告)日：2023-02-14

    申请号：US16938340

    申请日：2020-07-24

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Shih-Hao Lin ,  Tzu-Hsiang Hsu ,  Chong-De Lien ,  Szu-Chi Yang ,  Hsin-Wen Su ,  Chih-Hsiang Huang

    IPC: H01L21/8238 ,  H01L21/306 ,  H01L27/11 ,  H01L27/092

    Abstract: Semiconductor device and the manufacturing method thereof are disclosed herein. An exemplary method comprises forming first and second semiconductor fins in first and second regions of a substrate, respectively; forming first and second dummy gate stacks over the first and second semiconductor fins, respectively, and forming a spacer layer over the first and the second dummy gate stacks; forming a first pattern layer with a thickness along the spacer layer in the first region; form a first source/drain (S/D) trench along the first pattern layer and epitaxially growing a first epitaxial feature therein; removing the first pattern layer to expose the spacer layer; forming a second pattern layer with a different thickness along the spacer layer in the second region; form a second S/D trench along the second pattern layer and epitaxially growing a second epitaxial feature therein; and removing the second pattern layer to expose the spacer layer.

    Semiconductor Device With Tunable Epitaxy Structures And Method Of Forming The Same
    9.
    发明申请
    Semiconductor Device With Tunable Epitaxy Structures And Method Of Forming The Same 有权

    公开(公告)号：US20210098311A1

    公开(公告)日：2021-04-01

    申请号：US16938340

    申请日：2020-07-24

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Shih-Hao Lin ,  Tzu-Hsiang Hsu ,  Chong-De Lien ,  Szu-Chi Yang ,  Hsin-Wen Su ,  Chih-Hsiang Huang

    IPC: H01L21/8238 ,  H01L27/11 ,  H01L21/306

    Abstract: Semiconductor device and the manufacturing method thereof are disclosed herein. An exemplary method comprises forming first and second semiconductor fins in first and second regions of a substrate, respectively; forming first and second dummy gate stacks over the first and second semiconductor fins, respectively, and forming a spacer layer over the first and the second dummy gate stacks; forming a first pattern layer with a thickness along the spacer layer in the first region; form a first source/drain (S/D) trench along the first pattern layer and epitaxially growing a first epitaxial feature therein; removing the first pattern layer to expose the spacer layer; forming a second pattern layer with a different thickness along the spacer layer in the second region; form a second S/D trench along the second pattern layer and epitaxially growing a second epitaxial feature therein; and removing the second pattern layer to expose the spacer layer.

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