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公开(公告)号:US20240395902A1
公开(公告)日:2024-11-28
申请号:US18791056
申请日:2024-07-31
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor: Chien-Chih Lin , Yen-Ting Chen , Wen-Kai Lin , Szu-Chi Yang , Shih-Hao Lin , Tsung-Hung Lee , Ming-Lung Cheng
IPC: H01L29/66 , H01L21/02 , H01L21/8238 , H01L27/092 , H01L29/06 , H01L29/78
Abstract: In an embodiment, a structure includes: a semiconductor substrate; a fin extending from the semiconductor substrate; a gate stack over the fin; an epitaxial source/drain region in the fin adjacent the gate stack; and a gate spacer disposed between the epitaxial source/drain region and the gate stack, the gate spacer including a plurality of silicon oxycarbonitride layers, each of the plurality of silicon oxycarbonitride layers having a different concentration of silicon, a different concentration of oxygen, a different concentration of carbon, and a different concentration of nitrogen.
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公开(公告)号:US20240387274A1
公开(公告)日:2024-11-21
申请号:US18786886
申请日:2024-07-29
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor: Szu-Chi Yang , Allen Chien , Tsai-Yu Huang , Chien-Chih Lin , Po-Kai Hsiao , Shih-Hao Lin , Chien-Chih Lee , Chih Chieh Yeh , Cheng-Ting Ding , Tsung-Hung Lee
IPC: H01L21/8234 , H01L29/06 , H01L29/10
Abstract: A method according to the present disclosure includes providing a workpiece including a first fin-shaped structure and a second fin-shaped structure over a substrate, depositing a nitride liner over the substrate and sidewalls of the first fin-shaped structure and the second fin-shaped structure, forming an isolation feature over the nitride liner and between the first fin-shaped structure and the second fin-shaped structure, epitaxially growing a cap layer on exposed surfaces of the first fin-shaped structure and the second fin-shaped structure and above the nitride liner, crystalizing the cap layer, and forming a first source/drain feature over a first source/drain region of the first fin-shaped structure and a second source/drain feature over a second source/drain region of the second fin-shaped structure.
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公开(公告)号:US20210098305A1
公开(公告)日:2021-04-01
申请号:US16926528
申请日:2020-07-10
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor: Szu-Chi Yang , Allen Chien , Cheng-Ting Ding , Chien-Chih Lin , Chien-Chih Lee , Shih-Hao Lin , Tsung-Hung Lee , Chih Chieh Yeh , Po-Kai Hsiao , Tsai-Yu Huang
IPC: H01L21/8234 , H01L29/06 , H01L29/10
Abstract: The present disclosure provides methods of fabricating a semiconductor device. A method according to one embodiment includes forming, on a substrate, a first fin formed of a first semiconductor material and a second fin formed of a second semiconductor material different from the first semiconductor material, forming a semiconductor cap layer over the first fin and the second fin, and annealing the semiconductor cap layer at a first temperature while at least a portion of the semiconductor cap layer is exposed.
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公开(公告)号:US20240413018A1
公开(公告)日:2024-12-12
申请号:US18787277
申请日:2024-07-29
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd
Inventor: Shih-Hao Lin , Tzu-Hsiang Hsu , Chong-De Lien , Szu-Chi Yang , Hsin-Wen Su , Chih-Hsiang Huang
IPC: H01L21/8238 , H01L21/306 , H01L27/092 , H01L29/423 , H01L29/66 , H01L29/78 , H10B10/00
Abstract: Semiconductor device and the manufacturing method thereof are disclosed herein. An exemplary method comprises forming first and second semiconductor fins in first and second regions of a substrate, respectively; forming first and second dummy gate stacks over the first and second semiconductor fins, respectively, and forming a spacer layer over the first and the second dummy gate stacks; forming a first pattern layer with a thickness along the spacer layer in the first region; form a first source/drain (S/D) trench along the first pattern layer and epitaxially growing a first epitaxial feature therein; removing the first pattern layer to expose the spacer layer; forming a second pattern layer with a different thickness along the spacer layer in the second region; form a second S/D trench along the second pattern layer and epitaxially growing a second epitaxial feature therein; and removing the second pattern layer to expose the spacer layer.
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公开(公告)号:US12112989B2
公开(公告)日:2024-10-08
申请号:US17815085
申请日:2022-07-26
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor: Shih-Hao Lin , Tzu-Hsiang Hsu , Chong-De Lien , Szu-Chi Yang , Hsin-Wen Su , Chih-Hsiang Huang
IPC: H01L21/8238 , H01L21/306 , H01L27/092 , H01L29/423 , H01L29/66 , H01L29/78 , H10B10/00
CPC classification number: H01L21/823814 , H01L21/30604 , H01L21/823821 , H01L27/0924 , H01L29/42392 , H01L29/6656 , H01L29/7848 , H10B10/12
Abstract: Semiconductor device and the manufacturing method thereof are disclosed herein. An exemplary method comprises forming first and second semiconductor fins in first and second regions of a substrate, respectively; forming first and second dummy gate stacks over the first and second semiconductor fins, respectively, and forming a spacer layer over the first and the second dummy gate stacks; forming a first pattern layer with a thickness along the spacer layer in the first region; form a first source/drain (S/D) trench along the first pattern layer and epitaxially growing a first epitaxial feature therein; removing the first pattern layer to expose the spacer layer; forming a second pattern layer with a different thickness along the spacer layer in the second region; form a second S/D trench along the second pattern layer and epitaxially growing a second epitaxial feature therein; and removing the second pattern layer to expose the spacer layer.
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公开(公告)号:US20230326802A1
公开(公告)日:2023-10-12
申请号:US18329396
申请日:2023-06-05
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor: Szu-Chi Yang , Allen Chien , Tsai-Yu Huang , Chien-Chih Lin , Po-Kai Hsiao , Shih-Hao Lin , Chien-Chih Lee , Chih Chieh Yeh , Cheng-Ting Ding , Tsung-Hung Lee
IPC: H01L21/8234 , H01L29/06 , H01L29/10
CPC classification number: H01L21/823431 , H01L29/0607 , H01L21/823418 , H01L21/823412 , H01L29/1054
Abstract: The present disclosure provides methods of fabricating a semiconductor device. A method according to one embodiment includes forming, on a substrate, a first fin formed of a first semiconductor material and a second fin formed of a second semiconductor material different from the first semiconductor material, forming a semiconductor cap layer over the first fin and the second fin, and annealing the semiconductor cap layer at a first temperature while at least a portion of the semiconductor cap layer is exposed.
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公开(公告)号:US20220359308A1
公开(公告)日:2022-11-10
申请号:US17815085
申请日:2022-07-26
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor: Shih-Hao Lin , Tzu-Hsiang Hsu , Chong-De Lien , Szu-Chi Yang , Hsin-Wen Su , Chih-Hsiang Huang
IPC: H01L21/8238 , H01L21/306 , H01L27/11
Abstract: Semiconductor device and the manufacturing method thereof are disclosed herein. An exemplary method comprises forming first and second semiconductor fins in first and second regions of a substrate, respectively; forming first and second dummy gate stacks over the first and second semiconductor fins, respectively, and forming a spacer layer over the first and the second dummy gate stacks; forming a first pattern layer with a thickness along the spacer layer in the first region; form a first source/drain (S/D) trench along the first pattern layer and epitaxially growing a first epitaxial feature therein; removing the first pattern layer to expose the spacer layer; forming a second pattern layer with a different thickness along the spacer layer in the second region; form a second S/D trench along the second pattern layer and epitaxially growing a second epitaxial feature therein; and removing the second pattern layer to expose the spacer layer.
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公开(公告)号:US11949015B2
公开(公告)日:2024-04-02
申请号:US17885155
申请日:2022-08-10
Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
Inventor: Szu-Chi Yang , Chih-Hsiang Huang
IPC: H01L29/78 , H01L21/8234 , H01L21/8238 , H01L29/08 , H01L29/165 , H01L29/66
CPC classification number: H01L29/7851 , H01L21/823431 , H01L21/823821 , H01L29/0847 , H01L29/66795 , H01L29/7848 , H01L29/785 , H01L29/165
Abstract: A method includes following steps. A semiconductor fin is formed extending from a substrate. A gate structure is formed extending across the semiconductor fin. Recesses are etched in the semiconductor fin. Source/drain epitaxial structures are formed in the recesses in the semiconductor fin. Formation of each of the source/drain epitaxial structures comprises performing a first epitaxy growth process to form a bar-shaped epitaxial structure in one of the recesses, and performing a second epitaxy growth process to form a cladding epitaxial layer cladding on the bar-shaped epitaxial structure. The bar-shaped epitaxial structure has a lower phosphorous concentration than the cladding epitaxial layer.
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公开(公告)号:US11670551B2
公开(公告)日:2023-06-06
申请号:US16926528
申请日:2020-07-10
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor: Szu-Chi Yang , Allen Chien , Cheng-Ting Ding , Chien-Chih Lin , Chien-Chih Lee , Shih-Hao Lin , Tsung-Hung Lee , Chih Chieh Yeh , Po-Kai Hsiao , Tsai-Yu Huang
IPC: H01L21/8234 , H01L21/324 , H01L29/78 , H01L29/06 , H01L29/10
CPC classification number: H01L21/823431 , H01L21/823412 , H01L21/823418 , H01L29/0607 , H01L29/1054
Abstract: The present disclosure provides methods of fabricating a semiconductor device. A method according to one embodiment includes forming, on a substrate, a first fin formed of a first semiconductor material and a second fin formed of a second semiconductor material different from the first semiconductor material, forming a semiconductor cap layer over the first fin and the second fin, and annealing the semiconductor cap layer at a first temperature while at least a portion of the semiconductor cap layer is exposed.
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公开(公告)号:US11581226B2
公开(公告)日:2023-02-14
申请号:US16938340
申请日:2020-07-24
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor: Shih-Hao Lin , Tzu-Hsiang Hsu , Chong-De Lien , Szu-Chi Yang , Hsin-Wen Su , Chih-Hsiang Huang
IPC: H01L21/8238 , H01L21/306 , H01L27/11 , H01L27/092
Abstract: Semiconductor device and the manufacturing method thereof are disclosed herein. An exemplary method comprises forming first and second semiconductor fins in first and second regions of a substrate, respectively; forming first and second dummy gate stacks over the first and second semiconductor fins, respectively, and forming a spacer layer over the first and the second dummy gate stacks; forming a first pattern layer with a thickness along the spacer layer in the first region; form a first source/drain (S/D) trench along the first pattern layer and epitaxially growing a first epitaxial feature therein; removing the first pattern layer to expose the spacer layer; forming a second pattern layer with a different thickness along the spacer layer in the second region; form a second S/D trench along the second pattern layer and epitaxially growing a second epitaxial feature therein; and removing the second pattern layer to expose the spacer layer.
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