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    TRANSISTOR ISOLATION STRUCTURES
    11.
    发明申请
    TRANSISTOR ISOLATION STRUCTURES 有权

    公开(公告)号：US20220384576A1

    公开(公告)日：2022-12-01

    申请号：US17333276

    申请日：2021-05-28

    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

    Inventor： Chia-Ta YU ,  Yen-Chieh Huang ,  Yi-Hsien Tu ,  I-Hsieh Wong

    IPC: H01L29/10 ,  H01L29/66 ,  H01L29/167 ,  H01L21/761 ,  H01L27/092

    Abstract: The present disclosure is directed to methods for the fabrication of buried layers in gate-all-around (GAA) transistor structures to suppress junction leakage. In some embodiments, the method includes forming a doped epitaxial layer on a substrate, forming a stack of alternating first and second nano-sheet layers on the epitaxial layer, and patterning the stack and the epitaxial layer to form a fin structure. The method includes forming a sacrificial gate structure on the fin structure, removing portions of the fin structure not covered by the sacrificial gate structure, and etching portions of the first nano-sheet layers. Additionally, the method includes forming spacer structures on the etched portions of the first nano-sheet layers and forming source/drain (S/D) epitaxial structures on the epitaxial layer abutting the second nano-sheet layers. The method further includes removing the sacrificial gate structure, removing the first nano-sheet layers, and forming a gate structure around the second nano-sheet layers.

    Three dimensional metal insulator metal capacitor structure
    15.
    发明授权
    Three dimensional metal insulator metal capacitor structure 有权

    公开(公告)号：US11450733B2

    公开(公告)日：2022-09-20

    申请号：US16515915

    申请日：2019-07-18

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Sai-Hooi Yeong ,  Chia-Ta Yu ,  Yen-Chieh Huang

    IPC: H01L49/02 ,  H01L23/31 ,  H01L23/538 ,  H01L23/66 ,  H01L23/00

    Abstract: The present disclosure relates to a semiconductor device and a manufacturing method, and more particularly to a 3D metal insulator metal (MIM) capacitor structure with an increased capacitance per unit area in a semiconductor structure. The MIM structure includes a substrate, an oxide layer formed over the substrate, and a first metal layer formed over the oxide layer. The first metal layer includes a plurality of mandrels formed on a surface of the first metal layer. The MIM structure also includes a dielectric layer formed over the first metal layer and the plurality of mandrels, a second metal layer formed over on the dielectric layer, and one or more interconnect structures electrically connected to the first and second metal layers.

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