公开(公告)号：US11037818B2

公开(公告)日：2021-06-15

申请号：US16427088

申请日：2019-05-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Sai-Hooi Yeong ,  Yen-Chieh Huang

IPC: H01L21/82 ,  H01L21/764 ,  H01L29/78 ,  H01L29/06 ,  H01L29/66 ,  H01L29/08

Abstract: A semiconductor structure having epitaxial structures and a method for forming the same are provided. The method includes forming a gate structure over first and second fins on a semiconductor substrate. The method also includes forming a first dielectric material over the first and second fins and the gate structure. The method further includes forming a second dielectric material over the first dielectric material and above an interspace between the first and the second fins. The method includes partially removing the first dielectric material and the second dielectric material to form an inner spacer structure between the first fin and the second fin and outer spacers on two opposite sides of the inner spacer structure, wherein a top surface of the inner spacer structure is below top surfaces of the outer spacers. The method also includes forming an epitaxial structure on the first fin and the second fin.

公开(公告)号：US20220367608A1

公开(公告)日：2022-11-17

申请号：US17815105

申请日：2022-07-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Sai-Hooi YEONG ,  Chia-Ta Yu ,  Yen-Chieh Huang

IPC: H01L49/02 ,  H01L23/31 ,  H01L23/538 ,  H01L23/66 ,  H01L23/00

Abstract: The present disclosure relates to a semiconductor device and a manufacturing method, and more particularly to a 3D metal insulator metal (MIM) capacitor structure with an increased capacitance per unit area in a semiconductor structure. The MIM structure includes a substrate, an oxide layer formed over the substrate, and a first metal layer formed over the oxide layer. The first metal layer includes a plurality of mandrels formed on a surface of the first metal layer. The MIM structure also includes a dielectric layer formed over the first metal layer and the plurality of mandrels, a second metal layer formed over on the dielectric layer, and one or more interconnect structures electrically connected to the first and second metal layers.

公开(公告)号：US09335365B2

公开(公告)日：2016-05-10

申请号：US14724875

申请日：2015-05-29

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Yen-Chieh Huang ,  Ching-Huang Wang ,  Tsung-Yi Yu

IPC: G01R31/02 ,  G01R31/26 ,  G11C29/48 ,  G11C16/04 ,  G11C29/00 ,  G11C29/06 ,  G11C29/56 ,  H01L21/66

CPC classification number: G01R31/2644 ,  G01R31/26 ,  G01R31/2601 ,  G01R31/2642 ,  G11C16/0425 ,  G11C29/006 ,  G11C29/06 ,  G11C29/48 ,  G11C29/56008 ,  H01L22/34

Abstract: A method comprises providing first and second semiconductor devices. Each device comprises a transistor having a split gate electrode including first and second gate portions. Each device has a respective ratio between an area of its first gate portion and a sum of areas of its first and second gate portions. For each device, a stress voltage is applied to the first gate portion, but not to the second gate portion. For each device, the first and second gate portions are biased with a common voltage, and data are collected indicating a respective degradation for each device due to the stress voltage. The degradation has a component due to time dependent dielectric breakdown (TDDB) and a component due to bias temperature instability. From the collected data extrapolation determines the degradation component due to TDDB.

公开(公告)号：US12087811B2

公开(公告)日：2024-09-10

申请号：US17815105

申请日：2022-07-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Sai-Hooi Yeong ,  Chia-Ta Yu ,  Yen-Chieh Huang

IPC: H01L23/31 ,  H01L23/00 ,  H01L23/538 ,  H01L23/66 ,  H01L49/02

CPC classification number: H01L28/88 ,  H01L23/3128 ,  H01L23/5383 ,  H01L23/5386 ,  H01L23/5389 ,  H01L23/66 ,  H01L24/20 ,  H01L2223/6666 ,  H01L2224/214 ,  H01L2924/19041 ,  H01L2924/19105

Abstract: The present disclosure relates to a semiconductor device and a manufacturing method, and more particularly to a 3D metal insulator metal (MIM) capacitor structure with an increased capacitance per unit area in a semiconductor structure. The MIM structure includes a substrate, an oxide layer formed over the substrate, and a first metal layer formed over the oxide layer. The first metal layer includes a plurality of mandrels formed on a surface of the first metal layer. The MIM structure also includes a dielectric layer formed over the first metal layer and the plurality of mandrels, a second metal layer formed over on the dielectric layer, and one or more interconnect structures electrically connected to the first and second metal layers.

公开(公告)号：US11195951B2

公开(公告)日：2021-12-07

申请号：US16656619

申请日：2019-10-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chia-Ta Yu ,  Yen-Chieh Huang ,  Wei-Yuan Lu ,  Feng-Cheng Yang ,  Yen-Ming Chen

IPC: H01L29/78 ,  H01L27/088 ,  H01L21/8234 ,  H01L29/08 ,  H01L29/165

Abstract: A semiconductor device and method of manufacturing the semiconductor device are provided. An exemplary semiconductor device comprises a fin disposed over a substrate, wherein the fin includes a channel region and a source/drain region; a gate structure disposed over the substrate and over the channel region of the fin; a source/drain feature epitaxially grown in the source/drain region of the fin, wherein the source/drain feature includes a top epitaxial layer and a lower epitaxial layer formed below the top epitaxial layer, and the lower epitaxial layer includes a wavy top surface; and a contact having a wavy bottom surface matingly engaged with the wavy top surface of the lower epitaxial layer of the source/drain feature.

公开(公告)号：US20210020739A1

公开(公告)日：2021-01-21

申请号：US16515915

申请日：2019-07-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Sai-Hooi Yeong ,  Chia-Ta Yu ,  Yen-Chieh Huang

IPC: H01L49/02 ,  H01L23/31 ,  H01L23/538 ,  H01L23/00 ,  H01L23/66

Abstract: The present disclosure relates to a semiconductor device and a manufacturing method, and more particularly to a 3D metal insulator metal (MIM) capacitor structure with an increased capacitance per unit area in a semiconductor structure. The MIM structure includes a substrate, an oxide layer formed over the substrate, and a first metal layer formed over the oxide layer. The first metal layer includes a plurality of mandrels formed on a surface of the first metal layer. The MIM structure also includes a dielectric layer formed over the first metal layer and the plurality of mandrels, a second metal layer formed over on the dielectric layer, and one or more interconnect structures electrically connected to the first and second metal layers.

公开(公告)号：US11901415B2

公开(公告)日：2024-02-13

申请号：US17333276

申请日：2021-05-28

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chia-Ta Yu ,  Yen-Chieh Huang ,  Yi-Hsien Tu ,  I-Hsieh Wong

IPC: H01L29/10 ,  H01L29/66 ,  H01L29/167 ,  H01L21/761 ,  H01L27/092 ,  H01L21/8234 ,  H01L21/8238 ,  H01L27/088 ,  H01L21/02 ,  H01L29/423 ,  H01L29/06 ,  H01L29/786

CPC classification number: H01L29/1083 ,  H01L21/02378 ,  H01L21/761 ,  H01L21/823431 ,  H01L21/823821 ,  H01L27/0886 ,  H01L27/092 ,  H01L29/167 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/66553 ,  H01L21/0262 ,  H01L21/02532 ,  H01L21/02576 ,  H01L21/02579 ,  H01L29/0665 ,  H01L29/42392 ,  H01L29/78696

Abstract: The present disclosure is directed to methods for the fabrication of buried layers in gate-all-around (GAA) transistor structures to suppress junction leakage. In some embodiments, the method includes forming a doped epitaxial layer on a substrate, forming a stack of alternating first and second nano-sheet layers on the epitaxial layer, and patterning the stack and the epitaxial layer to form a fin structure. The method includes forming a sacrificial gate structure on the fin structure, removing portions of the fin structure not covered by the sacrificial gate structure, and etching portions of the first nano-sheet layers. Additionally, the method includes forming spacer structures on the etched portions of the first nano-sheet layers and forming source/drain (S/D) epitaxial structures on the epitaxial layer abutting the second nano-sheet layers. The method further includes removing the sacrificial gate structure, removing the first nano-sheet layers, and forming a gate structure around the second nano-sheet layers.

公开(公告)号：US20230387305A1

公开(公告)日：2023-11-30

申请号：US18447855

申请日：2023-08-10

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chia-Ta Yu ,  Yen-Chieh Huang ,  Wei-Yuan Lu ,  Feng-Cheng Yang ,  Yen-Ming Chen

IPC: H01L29/78 ,  H01L27/088 ,  H01L21/8234 ,  H01L29/08 ,  H01L29/165

CPC classification number: H01L29/7848 ,  H01L27/0886 ,  H01L29/7851 ,  H01L21/823418 ,  H01L29/0847 ,  H01L21/823431 ,  H01L29/165

Abstract: A semiconductor device and method of manufacturing the semiconductor device are provided. An exemplary semiconductor device comprises a fin disposed over a substrate, wherein the fin includes a channel region and a source/drain region; a gate structure disposed over the substrate and over the channel region of the fin; a source/drain feature epitaxially grown in the source/drain region of the fin, wherein the source/drain feature includes a top epitaxial layer and a lower epitaxial layer formed below the top epitaxial layer, and the lower epitaxial layer includes a wavy top surface; and a contact having a wavy bottom surface matingly engaged with the wavy top surface of the lower epitaxial layer of the source/drain feature.

公开(公告)号：US11824121B2

公开(公告)日：2023-11-21

申请号：US18190419

申请日：2023-03-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chia-Ta Yu ,  Yen-Chieh Huang ,  Wei-Yuan Lu ,  Feng-Cheng Yang ,  Yen-Ming Chen

IPC: H01L29/78 ,  H01L27/088 ,  H01L21/8234 ,  H01L29/08 ,  H01L29/165

CPC classification number: H01L29/7848 ,  H01L21/823418 ,  H01L21/823431 ,  H01L27/0886 ,  H01L29/0847 ,  H01L29/165 ,  H01L29/7851

Abstract: A semiconductor device and method of manufacturing the semiconductor device are provided. An exemplary semiconductor device comprises a fin disposed over a substrate, wherein the fin includes a channel region and a source/drain region; a gate structure disposed over the substrate and over the channel region of the fin; a source/drain feature epitaxially grown in the source/drain region of the fin, wherein the source/drain feature includes a top epitaxial layer and a lower epitaxial layer formed below the top epitaxial layer, and the lower epitaxial layer includes a wavy top surface; and a contact having a wavy bottom surface matingly engaged with the wavy top surface of the lower epitaxial layer of the source/drain feature.

公开(公告)号：US11616142B2

公开(公告)日：2023-03-28

申请号：US17542810

申请日：2021-12-06

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chia-Ta Yu ,  Yen-Chieh Huang ,  Wei-Yuan Lu ,  Feng-Cheng Yang ,  Yen-Ming Chen

IPC: H01L29/78 ,  H01L27/088 ,  H01L21/8234 ,  H01L29/08 ,  H01L29/165

Abstract: A semiconductor device and method of manufacturing the semiconductor device are provided. An exemplary semiconductor device comprises a fin disposed over a substrate, wherein the fin includes a channel region and a source/drain region; a gate structure disposed over the substrate and over the channel region of the fin; a source/drain feature epitaxially grown in the source/drain region of the fin, wherein the source/drain feature includes a top epitaxial layer and a lower epitaxial layer formed below the top epitaxial layer, and the lower epitaxial layer includes a wavy top surface; and a contact having a wavy bottom surface matingly engaged with the wavy top surface of the lower epitaxial layer of the source/drain feature.