公开(公告)号：US10565341B2

公开(公告)日：2020-02-18

申请号：US15878818

申请日：2018-01-24

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yen-Hung Lin ,  Chung-Hsing Wang ,  Yuan-Te Hou

IPC: G06F17/50

Abstract: The present disclosure describes an example method for cell placement in an integrated circuit layout design. The method includes retrieving, from a cell library, first and second cells each including a first local metal track proximate to a top boundary and a second local metal track proximate to a bottom boundary. The method includes placing, by a processor, the first and second cells in a layout area including global metal tracks of first and second types. Each global metal track of the first type and each global metal tracks of the second type alternate between one another in the layout area. The first and second local metal tracks of the first cell is aligned with adjacent first global metal track of the first and second types, respectively. The first and second local metal tracks of the second cell is aligned with adjacent second global metal track of the first and second types, respectively.

公开(公告)号：US20230153507A1

公开(公告)日：2023-05-18

申请号：US18096906

申请日：2023-01-13

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yen-Hung Lin ,  Yuan-Te Hou ,  Chung-Hsing Wang

IPC: G06F30/392 ,  G06F30/39

CPC classification number: G06F30/392 ,  G06F30/39 ,  G06F2119/12

Abstract: A partitioning method for partitioning a group of power-ground (PG) cells is disclosed. The method includes: placing at least one out-boundary PG cell on a substrate, wherein power strips of the at least one out-boundary PG cell are aligned with corresponding power rails on the substrate; and placing at least one in-boundary PG cell on the substrate, wherein power strips of the at least one in-boundary PG cell are aligned with corresponding power rails on the substrate.

公开(公告)号：US11574108B2

公开(公告)日：2023-02-07

申请号：US17363669

申请日：2021-06-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yen-Hung Lin ,  Yuan-Te Hou ,  Chung-Hsing Wang

IPC: G06F30/30 ,  G06F30/392 ,  G06F30/39 ,  G06F30/398 ,  G06F119/06 ,  G06F119/12

Abstract: A partitioning method for partitioning a group of power-ground (PG) cells is disclosed. The method includes: placing at least one out-boundary PG cell on a substrate, wherein power strips of the at least one out-boundary PG cell are aligned with corresponding power rails on the substrate; and placing at least one in-boundary PG cell on the substrate, wherein power strips of the at least one in-boundary PG cell are aligned with corresponding power rails on the substrate.

公开(公告)号：US10515175B2

公开(公告)日：2019-12-24

申请号：US15723308

申请日：2017-10-03

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yen-Hung Lin ,  Yuan-Te Hou ,  Chung-Hsing Wang

IPC: G06F17/50

Abstract: A partitioning method for partitioning a group of power-ground (PG) cells is disclosed. The method includes forming a first partition by selecting at least one in-boundary PG cell from the group of PG cells, adding at least one out-boundary PG cell from the group of PG cells into the first partition, forming a second partition by selecting the remaining in-boundary PG cells and the remaining out-boundary PG cells in the group of PG cells, calculating the total area of the in-boundary PG cells in the first partition, calculating the total area of the out-boundary PG cells in the first partition, calculating the total area of the in-boundary PG cells in the second partition, calculating the total area of the out-boundary PG cells in the second partition, and calculating the difference between the total areas of in-boundary PG cells in the first partition and the out-boundary PG cells in the first partition.

公开(公告)号：US11055466B2

公开(公告)日：2021-07-06

申请号：US16719481

申请日：2019-12-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yen-Hung Lin ,  Yuan-Te Hou ,  Chung-Hsing Wang

IPC: G06F30/30 ,  G06F30/392 ,  G06F30/39 ,  G06F30/398 ,  G06F119/06

Abstract: A partitioning method for partitioning a group of power-ground (PG) cells is disclosed. The method includes: placing at least one out-boundary PG cell on a substrate, wherein power strips of the at least one out-boundary PG cell are aligned with corresponding power rails on the substrate; and placing at least one in-boundary PG cell on the substrate, wherein power strips of the at least one in-boundary PG cell are aligned with corresponding power rails on the substrate.

公开(公告)号：US20200082046A1

公开(公告)日：2020-03-12

申请号：US16686711

申请日：2019-11-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yen-Hung Lin ,  Chung-Hsing Wang ,  Yuan-Te Hou

IPC: G06F17/50

Abstract: The present disclosure describes an example method for cell placement in an integrated circuit layout design. The method includes retrieving, from a cell library, first and second cells each including a first local metal track proximate to a top boundary and a second local metal track proximate to a bottom boundary. The method includes placing, by a processor, the first and second cells in a layout area including global metal tracks of first and second types. Each global metal track of the first type and each global metal tracks of the second type alternate between one another in the layout area. The first and second local metal tracks of the first cell is aligned with adjacent first global metal track of the first and second types, respectively. The first and second local metal tracks of the second cell is aligned with adjacent second global metal track of the first and second types, respectively.