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    CAPACITANCE REDUCTION BY METAL CUT DESIGN
    11.
    发明申请
    CAPACITANCE REDUCTION BY METAL CUT DESIGN 审中-公开

    公开(公告)号：US20200098631A1

    公开(公告)日：2020-03-26

    申请号：US16531232

    申请日：2019-08-05

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Yi-Hsiung Lin ,  Yu-Xuan Huang ,  Chih-Ming Lai ,  Ru-Gun Liu ,  Shang-Wen Chang ,  Yi-Hsun Chiu

    IPC: H01L21/768 ,  G06F17/50

    Abstract: The present disclosure describes a method for forming metal interconnects in an integrated circuit (IC). The method includes placing a metal interconnect in a layout area, determining a location of a redundant portion of the metal interconnect, and reducing, at the location, the length of the metal interconnect by a length of the redundant portion to form one or more active portions of the metal interconnect. The length of the redundant portion is a function of a distance between adjacent gate structures of the IC. The method further includes forming the one or more active portions on an interlayer dielectric (ILD) layer of the IC and forming vias on the one or more active portions, wherein the vias are positioned about 3 nm to about 5 nm away from an end of the one or more active portions.

    INTEGRATED CIRCUIT DEVICE INCLUDING A POWER SUPPLY LINE AND METHOD OF FORMING THE SAME
    13.
    发明申请
    INTEGRATED CIRCUIT DEVICE INCLUDING A POWER SUPPLY LINE AND METHOD OF FORMING THE SAME 有权

    公开(公告)号：US20240387530A1

    公开(公告)日：2024-11-21

    申请号：US18786788

    申请日：2024-07-29

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Yi-Hsiung Lin ,  Yi-Hsun Chiu ,  Shang-Wen Chang

    IPC: H01L27/088 ,  H01L21/8234 ,  H01L23/50 ,  H01L27/02

    Abstract: A device includes a first semiconductor strip and a second semiconductor strip extending longitudinally in a first direction, where the first semiconductor strip and the second semiconductor strip are spaced apart from each other in a second direction. The device also includes a power supply line located between the first semiconductor strip and the second semiconductor strip. A top surface of the power supply line is recessed in comparison to a top surface of the first semiconductor strip. A source feature is disposed on a source region of the first semiconductor strip, and a source contact electrically couples the source feature to the power supply line. The source contact includes a lateral portion contacting a top surface of the source feature, and a vertical portion extending along a sidewall of the source feature towards the power supply line to physically contact the power supply line.

    FINFET SRAM CELLS WITH REDUCED FIN PITCH
    15.
    发明申请
    FINFET SRAM CELLS WITH REDUCED FIN PITCH 有权

    公开(公告)号：US20220336472A1

    公开(公告)日：2022-10-20

    申请号：US17810673

    申请日：2022-07-05

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Chih-Hao Wang ,  Yi-Hsun Chiu ,  Yi-Hsiung Lin ,  Shang-Wen Chang

    IPC: H01L27/11 ,  H01L27/088 ,  H01L29/417 ,  H01L21/762 ,  H01L29/423

    Abstract: An integrated circuit (IC) includes a first p-type semiconductor fin, a first dielectric fin, a first hybrid fin, a second hybrid fin, a second dielectric fin, and a second p-type semiconductor fin disposed in this order along a first direction and oriented lengthwise along a second direction, where each of the first and the second hybrid fins has a first portion including an n-type semiconductor material and a second portion including a dielectric material. The IC further includes n-type source/drain (S/D) epitaxial features disposed over each of the first and the second p-type semiconductor fins, p-type S/D epitaxial features disposed over the first portion of each of the first and the second hybrid fins, and S/D contacts physically contacting each of the p-type S/D epitaxial features and the second portion of each of the first and the second hybrid fins.

    Capacitance reduction by metal cut design
    16.
    发明授权
    Capacitance reduction by metal cut design 有权

    公开(公告)号：US11004738B2

    公开(公告)日：2021-05-11

    申请号：US16531232

    申请日：2019-08-05

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Yi-Hsiung Lin ,  Yu-Xuan Huang ,  Chih-Ming Lai ,  Ru-Gun Liu ,  Shang-Wen Chang ,  Yi-Hsun Chiu

    IPC: H01L21/768 ,  G06F30/394

    Abstract: The present disclosure describes a method for forming metal interconnects in an integrated circuit (IC). The method includes placing a metal interconnect in a layout area, determining a location of a redundant portion of the metal interconnect, and reducing, at the location, the length of the metal interconnect by a length of the redundant portion to form one or more active portions of the metal interconnect. The length of the redundant portion is a function of a distance between adjacent gate structures of the IC. The method further includes forming the one or more active portions on an interlayer dielectric (ILD) layer of the IC and forming vias on the one or more active portions, wherein the vias are positioned about 3 nm to about 5 nm away from an end of the one or more active portions.

    IMPLANTER CALIBRATION
    17.
    发明申请
    IMPLANTER CALIBRATION 有权

    公开(公告)号：US20210043422A1

    公开(公告)日：2021-02-11

    申请号：US17080391

    申请日：2020-10-26

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Yi-Hsiung Lin ,  Cheng-En Lee ,  Chia-Lin Ou ,  Hsuan-Pang Liu ,  Yao-Jen Yeh

    IPC: H01J37/317 ,  H01J37/08 ,  H01J37/30

    Abstract: The present disclosure relates to a method includes generating ions with an ion source of an ion implantation apparatus based on an ion implantation recipe. The method includes accelerating the generated ions based on an ion energy setting in the ion implantation recipe and determining an energy spectrum of the accelerated ions. The method also includes analyzing a relationship between the determined energy spectrum and the ion energy setting. The method further includes adjusting at least one parameter of a final energy magnet (FEM) of the ion implantation apparatus based on the analyzed relationship.

    FinFET SRAM Cells with Reduced Fin Pitch
    18.
    发明申请
    FinFET SRAM Cells with Reduced Fin Pitch 审中-公开

    公开(公告)号：US20200098764A1

    公开(公告)日：2020-03-26

    申请号：US16526415

    申请日：2019-07-30

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Chih-Hao Wang ,  Yi-Hsun Chiu ,  Yi-Hsiung Lin ,  Shang-Wen Chang

    IPC: H01L27/11 ,  H01L27/088 ,  H01L29/423 ,  H01L29/417 ,  H01L21/762

    Abstract: A static random access memory (SRAM) cell includes a first p-type semiconductor fin, a first dielectric fin, a first hybrid fin, a second hybrid fin, a second dielectric fin, and a second p-type semiconductor fin disposed in this order along a first direction and oriented lengthwise along a second direction, where each of the first and the second hybrid fins has a first portion including an n-type semiconductor material and a second portion including a dielectric material. The SRAM cell further includes n-type source/drain (S/D) epitaxial features disposed over each of the first and the second p-type semiconductor fins, p-type S/D epitaxial features disposed over the first portion of each of the first and the second hybrid fins, and S/D contacts physically contacting each of the p-type S/D epitaxial features and the second portion of each of the first and the second hybrid fins.

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