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公开(公告)号：US20240363626A1
公开(公告)日：2024-10-31
申请号：US18766867
申请日：2024-07-09
IPC分类号： H01L27/088 , H01L21/768 , H01L23/535 , H01L29/417 , H01L29/423 , H01L29/66 , H01L29/78
CPC分类号： H01L27/0886 , H01L21/7682 , H01L23/535 , H01L29/41791 , H01L29/42392 , H01L29/66795 , H01L29/7851
摘要： Methods of performing backside etching processes on source/drain regions and gate structures of semiconductor devices and semiconductor devices formed by the same are disclosed. In an embodiment, a semiconductor device includes a first transistor structure; a first interconnect structure on a front-side of the first transistor structure; and a second interconnect structure on a backside of the first transistor structure, the second interconnect structure including a first dielectric layer on the backside of the first transistor structure; a contact extending through the first dielectric layer to a source/drain region of the first transistor structure; and first spacers along sidewalls of the contact between the contact and the first dielectric layer, sidewalls of the first spacers facing the first dielectric layer being aligned with sidewalls of the source/drain region of the first transistor structure.
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公开(公告)号：US20240312913A1
公开(公告)日：2024-09-19
申请号：US18184085
申请日：2023-03-15
IPC分类号： H01L23/528 , H01L21/78 , H01L21/8238 , H01L27/092 , H01L29/417 , H01L29/66 , H01L29/78
CPC分类号： H01L23/5286 , H01L21/7806 , H01L21/823814 , H01L21/823871 , H01L21/823885 , H01L27/092 , H01L29/41741 , H01L29/66666 , H01L29/7827
摘要： A method includes forming a vertical transistor, and the method includes forming a vertical semiconductor bar over a substrate, forming a gate dielectric and a gate electrode encircling the vertical semiconductor bar, forming a first source/drain region over a top surface of the vertical semiconductor bar, removing the substrate to reveal a bottom surface of the vertical semiconductor bar; and forming a second source/drain region contacting the bottom surface of the vertical semiconductor bar. The method further includes forming a backside power line, with the backside power line being on a bottom side of the vertical semiconductor bar. The backside power line is connected to the second source/drain region.
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公开(公告)号：US20230369324A1
公开(公告)日：2023-11-16
申请号：US18358140
申请日：2023-07-25
IPC分类号： H01L27/088 , H01L21/768 , H01L29/78 , H01L29/423 , H01L29/417 , H01L29/66 , H01L23/535
CPC分类号： H01L27/0886 , H01L21/7682 , H01L29/7851 , H01L29/42392 , H01L29/41791 , H01L29/66795 , H01L23/535
摘要： Methods of performing backside etching processes on source/drain regions and gate structures of semiconductor devices and semiconductor devices formed by the same are disclosed. In an embodiment, a semiconductor device includes a first transistor structure; a first interconnect structure on a front-side of the first transistor structure; and a second interconnect structure on a backside of the first transistor structure, the second interconnect structure including a first dielectric layer on the backside of the first transistor structure; a contact extending through the first dielectric layer to a source/drain region of the first transistor structure; and first spacers along sidewalls of the contact between the contact and the first dielectric layer, sidewalls of the first spacers facing the first dielectric layer being aligned with sidewalls of the source/drain region of the first transistor structure.
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公开(公告)号：US20230326808A1
公开(公告)日：2023-10-12
申请号：US18336168
申请日：2023-06-16
发明人： Yi-Hsiung Lin , Yi-Hsun Chiu , Shang-Wen Chang
IPC分类号： H01L21/8238 , H01L23/522 , H01L27/092 , H01L21/768 , H01L29/08 , H01L29/66 , H01L21/762 , H01L29/78
CPC分类号： H01L21/823871 , H01L21/823814 , H01L23/5226 , H01L27/0924 , H01L21/76831 , H01L29/0847 , H01L29/6681 , H01L21/76224 , H01L29/7851 , H01L21/823821 , H01L21/76832 , H01L21/823878 , H01L2029/7858
摘要： A semiconductor structure includes a first semiconductor fin and a second semiconductor fin adjacent to the first semiconductor fin. The first and the second semiconductor fins extend lengthwise along a first direction over a substrate. A metal gate structure is disposed over the first and second semiconductor fins, the metal gate structure extending lengthwise along a second direction perpendicular to the first direction. A first epitaxial source/drain (S/D) feature is disposed over the first semiconductor fin, and a second epitaxial S/D feature is disposed over the second semiconductor fin. An interlayer dielectric (ILD) layer is disposed over the first and the second epitaxial S/D features. And an S/D contact is disposed directly above the first and second epitaxial S/D features. The S/D contact directly contacts the first epitaxial S/D feature, and the S/D contact is isolated from the second epitaxial S/D feature by the ILD layer.
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公开(公告)号：US11532703B2
公开(公告)日：2022-12-20
申请号：US17127095
申请日：2020-12-18
发明人： Huan-Chieh Su , Cheng-Chi Chuang , Shang-Wen Chang , Yi-Hsun Chiu , Pei-Yu Wang , Ching-Wei Tsai , Chih-Hao Wang
IPC分类号： H01L29/06 , H01L27/092 , H01L21/8234 , H01L29/66 , H01L29/78 , H01L23/538
摘要： In an embodiment, a device includes: a power rail contact; an isolation region on the power rail contact; a first dielectric fin on the isolation region; a second dielectric fin adjacent the isolation region and the power rail contact; a first source/drain region on the second dielectric fin; and a source/drain contact between the first source/drain region and the first dielectric fin, the source/drain contact contacting a top surface of the first source/drain region, a side surface of the first source/drain region, and a top surface of the power rail contact.
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公开(公告)号：US11315936B2
公开(公告)日：2022-04-26
申请号：US16805868
申请日：2020-03-02
发明人： Meng-Sheng Chang , Chia-En Huang , Yi-Hsun Chiu , Yih Wang
IPC分类号： H01L29/66 , H01L21/84 , H01L27/112 , H01L23/525
摘要： A memory device and a manufacturing method thereof are provided. The memory device includes a transistor, a first embedded insulating structure and a second embedded insulating structure. The transistor is formed on a substrate, and includes a gate structure, channel structures, a source electrode and a drain electrode. The channel structures penetrate through the gate structure, and are in contact with the source and drain electrodes. The first and second embedded insulating structures are disposed in the substrate, and overlapped with the source and drain electrodes. The first and second embedded insulating structures are laterally spaced apart from each other by a portion of the substrate lying under the gate structure.
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公开(公告)号：US20210343712A1
公开(公告)日：2021-11-04
申请号：US17373255
申请日：2021-07-12
发明人： Yi-Hsiung Lin , Shang-Wen Chang , Yi-Hsun Chiu
IPC分类号： H01L27/088 , H01L21/8234 , H01L27/02 , H01L23/50
摘要： A device includes a first semiconductor strip and a second semiconductor strip extending longitudinally in a first direction, where the first semiconductor strip and the second semiconductor strip are spaced apart from each other in a second direction. The device also includes a power supply line located between the first semiconductor strip and the second semiconductor strip. A top surface of the power supply line is recessed in comparison to a top surface of the first semiconductor strip. A source feature is disposed on a source region of the first semiconductor strip, and a source contact electrically couples the source feature to the power supply line. The source contact includes a lateral portion contacting a top surface of the source feature, and a vertical portion extending along a sidewall of the source feature towards the power supply line to physically contact the power supply line.
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公开(公告)号：US20210335783A1
公开(公告)日：2021-10-28
申请号：US16944025
申请日：2020-07-30
IPC分类号： H01L27/088 , H01L29/78 , H01L29/423 , H01L23/535 , H01L29/417 , H01L29/66 , H01L21/768
摘要： Methods of performing backside etching processes on source/drain regions and gate structures of semiconductor devices and semiconductor devices formed by the same are disclosed. In an embodiment, a semiconductor device includes a first transistor structure; a first interconnect structure on a front-side of the first transistor structure; and a second interconnect structure on a backside of the first transistor structure, the second interconnect structure including a first dielectric layer on the backside of the first transistor structure; a contact extending through the first dielectric layer to a source/drain region of the first transistor structure; and first spacers along sidewalls of the contact between the contact and the first dielectric layer, sidewalls of the first spacers facing the first dielectric layer being aligned with sidewalls of the source/drain region of the first transistor structure.
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公开(公告)号：US11081403B2
公开(公告)日：2021-08-03
申请号：US16393543
申请日：2019-04-24
发明人： Yi-Hsiung Lin , Yi-Hsun Chiu , Shang-Wen Chang
IPC分类号： H01L21/768 , H01L21/762 , H01L21/8238 , H01L27/092 , H01L29/08 , H01L29/66 , H01L29/78 , H01L23/522
摘要： A method includes forming an interlayer dielectric (ILD) layer over a first epitaxial source/drain (S/D) feature and a second epitaxial S/D feature, where the first epitaxial S/D feature is disposed adjacent to the second epitaxial S/D feature, forming a dummy contact feature in the ILD layer over the first epitaxial S/D feature, removing a portion of the dummy contact feature and a portion of the ILD layer disposed above the second epitaxial S/D feature to form a first trench, removing a remaining portion of the dummy contact feature to form a second trench, and forming a metal S/D contact in the first and the second trenches.
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公开(公告)号：US10672665B2
公开(公告)日：2020-06-02
申请号：US16251642
申请日：2019-01-18
发明人： Shang-Wen Chang , Yi-Hsiung Lin , Yi-Hsun Chiu
IPC分类号： H01L21/8234 , H01L29/66 , H01L29/78 , H01L27/088 , H01L21/768
摘要： A method for forming a FinFET device structure includes forming a first fin structure and a second fin structure on a substrate. The method also includes depositing a first spacer layer over the first and second fin structures. The method also includes growing a power rail between the bottom portion of the first fin structure and the bottom portion of the second fin structure. The method also includes forming a second spacer layer over the sidewalls of the first spacer layer and over the top surface of the power rail. The method also includes forming a first fin isolation structure over the power rail between the first and second fin structures. The method also includes forming a first contact structure over the first fin structure and a portion of the power rail. The method also includes forming a second contact structure over the second fin structure.
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