公开(公告)号：US20240258237A1

公开(公告)日：2024-08-01

申请号：US18633002

申请日：2024-04-11

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Pei-Yu Wang ,  Yu-Xuan Huang

IPC: H01L23/528 ,  H01L21/02 ,  H01L21/285 ,  H01L21/311 ,  H01L29/06 ,  H01L29/417 ,  H01L29/423 ,  H01L29/45 ,  H01L29/66 ,  H01L29/78 ,  H01L29/786

CPC classification number: H01L23/5286 ,  H01L21/02603 ,  H01L21/28518 ,  H01L21/31116 ,  H01L21/31144 ,  H01L29/0673 ,  H01L29/41733 ,  H01L29/42392 ,  H01L29/45 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/66636 ,  H01L29/66742 ,  H01L29/7848 ,  H01L29/78618 ,  H01L29/78696

Abstract: In an embodiment, a device includes: a first fin; a gate structure over the first fin; a first source/drain region adjacent the gate structure; an etch stop layer over the first source/drain region; a conductive line over the etch stop layer, the conductive line isolated from the first source/drain region by the etch stop layer, a top surface of the conductive line being coplanar with a top surface of the gate structure; and a power rail contact extending through the first fin, the power rail contact connected to the first source/drain region.

公开(公告)号：US20240250032A1

公开(公告)日：2024-07-25

申请号：US18308355

申请日：2023-04-27

Applicant: Taiwan Semiconductor Manufacturing Co,. Ltd.

Inventor： Kuo-Cheng Chiang ,  Chih-Hao Wang ,  Guan-Lin Chen ,  Yu-Xuan Huang ,  Jin Cai

IPC: H01L23/535 ,  H01L21/8238 ,  H01L23/528 ,  H01L27/092 ,  H01L29/06 ,  H01L29/417 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775

CPC classification number: H01L23/535 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823871 ,  H01L21/823885 ,  H01L23/5286 ,  H01L27/092 ,  H01L29/0673 ,  H01L29/41733 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/775

Abstract: In an embodiment, a device includes: a lower source/drain region; an upper source/drain region; a nanostructure between the upper source/drain region and the lower source/drain region; a gate structure extending into a sidewall of the nanostructure, the gate structure including a gate dielectric and a gate electrode, an outer sidewall of the gate electrode being aligned with an outer sidewall of the gate dielectric; and a gate contact adjacent the gate structure, the gate contact extending along the outer sidewall of the gate electrode and the outer sidewall of the gate dielectric.

公开(公告)号：US11973075B2

公开(公告)日：2024-04-30

申请号：US17181196

申请日：2021-02-22

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tao Yi Hung ,  Yu-Xuan Huang ,  Kuo-Ji Chen

IPC: H01L27/02 ,  H01L23/528

CPC classification number: H01L27/0255 ,  H01L23/5286 ,  H01L27/0292

Abstract: An ESD protection device includes a PN diode formed in a semiconductor body. The PN diode has a first contact coupled to a metal structure on a front side of the semiconductor body and a second contact coupled to a metal structure on a back side of the semiconductor body. The metal coupled to the first contact is spaced apart from the metal coupled to the second contact by a thickness of the semiconductor body. This spacing greatly reduces the capacitance associated with the metal structures, which can substantially reduce the overall capacitance added to an I/O channel by the ESD protection device and thereby improve the performance of a high-speed circuit that uses the I/O channel.

公开(公告)号：US11532556B2

公开(公告)日：2022-12-20

申请号：US16947390

申请日：2020-07-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu-Xuan Huang ,  Ching-Wei Tsai ,  Cheng-Ting Chung ,  Cheng-Chi Chuang ,  Shang-Wen Chang

IPC: H01L21/8234 ,  H01L23/528 ,  H01L27/088 ,  H01L29/78 ,  H01L29/66

Abstract: The present disclosure provides one embodiment of a semiconductor structure. The semiconductor structure includes a substrate having a front side and a back side; a gate stack formed on the front side of the substrate and disposed on an active region of the substrate; a first source/drain feature formed on the active region and disposed at an edge of the gate stack; a backside power rail formed on the back side of the substrate; and a backside contact feature interposed between the backside power rail and the first source/drain feature, and electrically connecting the backside power rail to the first source/drain feature. The backside contact feature further includes a first silicide layer on the back side of the substrate.

公开(公告)号：US11342326B2

公开(公告)日：2022-05-24

申请号：US16944025

申请日：2020-07-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yi-Hsun Chiu ,  Ching-Wei Tsai ,  Yu-Xuan Huang ,  Cheng-Chi Chuang ,  Shang-Wen Chang

IPC: H01L27/088 ,  H01L29/78 ,  H01L29/423 ,  H01L21/768 ,  H01L29/417 ,  H01L29/66 ,  H01L23/535

Abstract: Methods of performing backside etching processes on source/drain regions and gate structures of semiconductor devices and semiconductor devices formed by the same are disclosed. In an embodiment, a semiconductor device includes a first transistor structure; a first interconnect structure on a front-side of the first transistor structure; and a second interconnect structure on a backside of the first transistor structure, the second interconnect structure including a first dielectric layer on the backside of the first transistor structure; a contact extending through the first dielectric layer to a source/drain region of the first transistor structure; and first spacers along sidewalls of the contact between the contact and the first dielectric layer, sidewalls of the first spacers facing the first dielectric layer being aligned with sidewalls of the source/drain region of the first transistor structure.

公开(公告)号：US20210367050A1

公开(公告)日：2021-11-25

申请号：US17397596

申请日：2021-08-09

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ching-Wei Tsai ,  Yi-Bo Liao ,  Cheng-Ting Chung ,  Yu-Xuan Huang ,  Kuan-Lun Cheng

IPC: H01L29/417 ,  H01L29/45 ,  H01L29/40 ,  H01L29/66 ,  H01L29/78

Abstract: A semiconductor device includes a first source/drain region and a second source/drain region disposed on opposite sides of a plurality of conductive layers. A dielectric layer overlies the first source/drain region, the second source/drain region, and the plurality of conductive layers. An electrical contact extends through the dielectric layer and the first source/drain region, where a first surface of the electrical contact is a surface of the electrical contact that is closest to the substrate, a first surface of the plurality of conductive layers is a surface of the plurality of conductive layers that is closest to the substrate, and the first surface of the electrical contact is closer to the substrate than the first surface of the plurality of conductive layers.

公开(公告)号：US20210366906A1

公开(公告)日：2021-11-25

申请号：US17116552

申请日：2020-12-09

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu-Xuan Huang ,  Chia-En Huang ,  Ching-Wei Tsai ,  Kuan-Lun Cheng

IPC: H01L27/092 ,  H01L21/8238 ,  H01L29/06 ,  H01L29/423 ,  H01L23/528

Abstract: A semiconductor structure includes a power rail, a first source/drain feature disposed over the power rail, a via connecting the power rail to the first source/drain feature; an isolation feature disposed over the first source/drain feature, and a second source/drain feature disposed over the isolation feature, where the first and the second source/drain features are of opposite conductivity types.

公开(公告)号：US20210343639A1

公开(公告)日：2021-11-04

申请号：US17158409

申请日：2021-01-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Pei-Yu Wang ,  Yu-Xuan Huang

IPC: H01L23/522 ,  H01L27/088 ,  H01L21/768

Abstract: An integrated circuit (IC) structure includes a gate structure, a source epitaxial structure, a drain epitaxial structure, a front-side interconnection structure, a backside dielectric layer, an epitaxial regrowth layer, and a backside via. The source epitaxial structure and the drain epitaxial structure are respectively on opposite sides of the gate structure. The front-side interconnection structure is over a front-side of the source epitaxial structure and a front-side of the drain epitaxial structure. The backside dielectric layer is over a backside of the source epitaxial structure and a backside of the drain epitaxial structure. The epitaxial regrowth layer is on the backside of a first one of the source epitaxial structure and the drain epitaxial structure. The backside via extends through the backside dielectric layer and overlaps the epitaxial regrowth layer.

公开(公告)号：US20210234047A1

公开(公告)日：2021-07-29

申请号：US16947372

申请日：2020-07-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ching-Wei Tsai ,  Yi-Bo Liao ,  Sai-Hooi Yeong ,  Hou-Yu Chen ,  Yu-Xuan Huang ,  Kuan-Lun Cheng

IPC: H01L29/786 ,  H01L29/06 ,  H01L29/10 ,  H01L29/423 ,  H01L21/02 ,  H01L21/324 ,  H01L29/66

Abstract: A semiconductor device according to the present disclosure includes an anti-punch-through (APT) region over a substrate, a plurality of channel members over the APT region, a gate structure wrapping around each of the plurality of channel members, a source/drain feature adjacent to the gate structure, and a diffusion retardation layer. The source/drain feature is spaced apart from the APT region by the diffusion retardation layer. The source/drain feature is spaced apart from each of the plurality of channel members by the diffusion retardation layer. The diffusion retardation layer is a semiconductor material.

公开(公告)号：US20250142950A1

公开(公告)日：2025-05-01

申请号：US19004755

申请日：2024-12-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu-Xuan Huang ,  Ching-Wei Tsai ,  Jam-Wem Lee ,  Kuo-Ji Chen ,  Kuan-Lun Cheng

IPC: H10D84/83 ,  H10D30/01 ,  H10D30/62 ,  H10D62/10 ,  H10D84/80

Abstract: The present disclosure provides embodiments of semiconductor devices. A semiconductor device according to the present disclosure include an elongated semiconductor member surrounded by an isolation feature and extending lengthwise along a first direction, a first source/drain feature and a second source/drain feature over a top surface of the elongated semiconductor member, a vertical stack of channel members each extending lengthwise between the first source/drain feature and the second source/drain feature along the first direction, a gate structure wrapping around each of the channel members, an epitaxial layer deposited on the bottom surface of the elongated semiconductor member, a silicide layer disposed on the epitaxial layer, and a conductive layer disposed on the silicide layer.