公开(公告)号：US20140157088A1

公开(公告)日：2014-06-05

申请号：US13917772

申请日：2013-06-14

Applicant: Taiwan Semiconductor Manufacturing Co. Ltd.

Inventor： Yue-Der Chih ,  Hung-Chang Yu ,  Kai-Chun Lin ,  Chin-Yi Huang ,  Laun C. Tran

IPC: G06F11/10 ,  G06F11/14

CPC classification number: G06F11/1056 ,  G06F11/10 ,  G06F11/1004 ,  G06F11/1048 ,  G06F11/1052 ,  G06F11/1402 ,  G06F11/141 ,  G11C11/1675 ,  G11C11/1677 ,  G11C2013/0076 ,  H03M13/11 ,  H03M13/611

Abstract: Some aspects of the present disclosure relate a method. The method attempts to write an expected multi-bit word to a memory location in memory. After writing of the multi-bit word has been attempted, an actual multi-bit word is read from the memory location. The actual multi-bit word is then compared with the expected multi-bit word to identify a number of erroneous bits and a number of correct bits stored in the memory location. The number of erroneous bits is re-written to the memory location without attempting to re-write the correct bits to the memory location.

Abstract translation: 本公开的一些方面涉及一种方法。 该方法尝试将期望的多位字写入存储器中的存储器位置。 在尝试写入多位字之后，从存储器位置读取实际的多位字。 然后将实际的多位字与期望的多位字进行比较，以识别存储在存储器位置中的错误位数和数量的正确位。 错误位的数量被重写到存储器位置，而不尝试将正确的位重写到存储器位置。

公开(公告)号：US10714535B2

公开(公告)日：2020-07-14

申请号：US16230798

申请日：2018-12-21

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Ku-Feng Lin ,  Hung-Chang Yu ,  Kai-Chun Lin ,  Yu-Der Chih

IPC: H01L27/24 ,  H01L45/00 ,  H01L23/48 ,  H01L23/522 ,  H01L23/528 ,  H01L25/18 ,  H01L27/088 ,  H01L23/532

Abstract: A method includes forming an insulator over a substrate. The insulator includes a first electrode, a second electrode, and a resistive element between the first electrode and the second electrode. The insulator is transformed into a resistor by applying a voltage to the insulator. The resistor is electrically connected to a transistor after transforming the insulator into the resistor.

公开(公告)号：US09165629B2

公开(公告)日：2015-10-20

申请号：US13804773

申请日：2013-03-14

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yue-Der Chih ,  Kai-Chun Lin ,  Hung-Chang Yu

IPC: G11C11/00 ,  G11C11/16 ,  G11C7/14 ,  G11C29/02

CPC classification number: G11C11/1673 ,  G11C7/14 ,  G11C11/1675 ,  G11C29/021 ,  G11C29/028

Abstract: A trimming process for setting a reference current used in operating an MRAM module comprising an operational MRAM cell coupled to a bit line, multiple reference MRAM cells coupled to a reference bit line, and a sense amplifier coupled to the bit line and the reference bit line is disclosed in some embodiments. The process includes applying a bit line reference voltage to the reference bit line to provide a reference cell current formed by a sum of respective currents through the plurality of reference MRAM cells. The reference cell current is detected. A determination is made as to whether the detected reference cell current differs from a target reference cell current. The bit line reference voltage is varied, or a sensing ratio of the sense amplifier is varied, if it is determined that the detected reference cell current differs from the target reference cell current.

Abstract translation: 一种用于设置用于操作MRAM模块的参考电流的修整过程，该MRAM模块包括耦合到位线的操作MRAM单元，耦合到参考位线的多个参考MRAM单元以及耦合到位线和参考位线的读出放大器 在一些实施例中被公开。 该过程包括将位线参考电压施加到参考位线以提供通过多个参考MRAM单元的相应电流之和形成的参考单元电流。 检测参考单元电流。 确定检测到的参考单元电流是否与目标参考单元电流不同。 如果确定检测到的参考单元电流与目标参考单元电流不同，则位线参考电压被改变，或者感测放大器的感测比是变化的。