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    MEMORY CONTROLLER, NONVOLATILE STORAGE DEVICE, NONVOLATILE STORAGE SYSTEM, AND NONVOLATILE MEMORY ADDRESS MANAGEMENT METHOD
    11.
    发明申请
    MEMORY CONTROLLER, NONVOLATILE STORAGE DEVICE, NONVOLATILE STORAGE SYSTEM, AND NONVOLATILE MEMORY ADDRESS MANAGEMENT METHOD 失效
    存储器控制器，非易失性存储设备，非易失性存储系统和非易失性存储器地址管理方法

    公开(公告)号：US20090055618A1

    公开(公告)日：2009-02-26

    申请号：US11814202

    申请日：2006-07-21

    申请人： Masahiro Nakanishi ,  Tetsushi Kasahara ,  Tomoaki Izumi ,  Kiminori Matsuno ,  Daisuke Kunimune ,  Kazuaki Tamura ,  Yoshiyuki Konishi

    发明人： Masahiro Nakanishi ,  Tetsushi Kasahara ,  Tomoaki Izumi ,  Kiminori Matsuno ,  Daisuke Kunimune ,  Kazuaki Tamura ,  Yoshiyuki Konishi

    IPC分类号： G06F12/02 ,  G06F12/00 ,  G06F12/06

    CPC分类号： G06F12/0246 ,  G06F2212/1036 ,  G06F2212/7211

    摘要： For address management of a nonvolatile memory, the whole logical address space is divided into logical address ranges (0 to 15), and the physical address space is divided into physical areas (segments (0 to 15)). The logical address ranges are respectively associated with the physical areas (segments) to manage the addresses. The sizes of the logical address ranges are equalized. The size of the physical area (segment (0)) corresponding to the logical address range (0) in which data of high rewrite frequency such as an FAT is expected to be stored is larger than those of the other physical areas, and the logical address ranges and the physical areas are allocated. Alternatively, the sizes of the physical areas are equalized, and the size of the logical address range (0) is set as a smaller one than those of the other logical address ranges. With this, the actual rewrite frequencies of the physical areas (segments) are equal to one another, and consequently the life of the nonvolatile memory can be prolonged.

    摘要翻译： 对于非易失性存储器的地址管理，整个逻辑地址空间被划分为逻辑地址范围（0至15），物理地址空间被划分为物理区域（段（0至15））。 逻辑地址范围分别与物理区域（段）相关联以管理地址。 逻辑地址范围的大小相等。 对应于期望存储诸如FAT的高重写频率的数据的逻辑地址范围（0）的物理区域（段（0））的大小大于其他物理区域的大小，并且逻辑 地址范围和物理区域被分配。 或者，物理区域的大小相等，并且逻辑地址范围（0）的大小被设置为比其他逻辑地址范围的大小小。 由此，物理区域（段）的实际重写频率彼此相等，因此可以延长非易失性存储器的寿命。

    STORAGE DEVICE
    12.
    发明申请
    STORAGE DEVICE 有权
    储存设备

    公开(公告)号：US20090019194A1

    公开(公告)日：2009-01-15

    申请号：US11909749

    申请日：2006-03-24

    申请人： Masayuki Toyama ,  Masahiro Nakanishi ,  Tomoaki Izumi ,  Tetsushi Kasahara ,  Kazuaki Tamura ,  Kiminori Matsuno ,  Manabu Inoue

    发明人： Masayuki Toyama ,  Masahiro Nakanishi ,  Tomoaki Izumi ,  Tetsushi Kasahara ,  Kazuaki Tamura ,  Kiminori Matsuno ,  Manabu Inoue

    IPC分类号： G06F3/00

    CPC分类号： G06F3/0659 ,  G06F3/061 ,  G06F3/0656 ,  G06F3/0658 ,  G06F3/0676 ,  G06F11/1441

    摘要： When a control unit (160) in a storage device (100) detects that a write end command or a data amount to be written has been transmitted from a host device (110), the control unit (160) saves control information required for writing data in a control information save memory (142). The control unit (160) also saves data which has not been written in storage medium into a buffer save memory (152) from a data buffer (151) and releases the busy state for the host device (110). The control unit (160) writes the saved data into a storage medium (120). Even if the power is turned OFF before completion of write, write can be performed into the storage medium (120) by using the saved data when the power is turned ON next time.

    摘要翻译： 当存储装置（100）中的控制单元（160）检测到从主机（110）发送写入结束命令或写入数据量时，控制单元（160）保存写入所需的控制信息 控制信息中的数据保存存储器（142）。 控制单元（160）还将从存储介质中未被写入的数据从数据缓冲器（151）保存到缓冲存储器（152）中，并且释放主机设备（110）的忙状态。 控制单元（160）将保存的数据写入存储介质（120）。 即使在完成写入之前电源被关闭，当下一次接通电源时，也可以通过使用保存的数据来对存储介质（120）进行写入。

    Semiconductor memory device, controller, and read/write control method thereof
    13.
    发明申请
    Semiconductor memory device, controller, and read/write control method thereof 有权
    半导体存储器件，控制器及其读/写控制方法

    公开(公告)号：US20060190670A1

    公开(公告)日：2006-08-24

    申请号：US10553974

    申请日：2004-10-13

    申请人： Masahiro Nakanishi ,  Tomoaki Izumi ,  Tetsushi Kasahara ,  Kazuaki Tamura ,  Kiminori Matsuno

    发明人： Masahiro Nakanishi ,  Tomoaki Izumi ,  Tetsushi Kasahara ,  Kazuaki Tamura ,  Kiminori Matsuno

    IPC分类号： G06F12/06 ,  G06F12/00

    CPC分类号： G06F12/06 ,  G06F2212/2022

    摘要： A controller 102 and four flash memories F0 to F3 are connected by twos to two memory buses, and each flash memory is divided into two regions of substantially the same size to form a first half and a last half regions. In a four-memory configuration, a consecutive logical address specified by a host apparatus is divided into a predetermined size, and a write operation is performed in a format that repeatedly circulates through F0, F1, F2, F3 in this order. In a two-memory configuration, the write operation is performed in a format that repeatedly circulates through F00, F10, F01, F11. Thus, a controller processing is made common regardless of the number of flash memories connected to the controller.

    摘要翻译： 控制器102和四个闪速存储器F 0至F 3通过两个连接到两个存储器总线，并且每个闪速存储器被划分为大致相同大小的两个区域，以形成前半部分和后半个区域。 在四存储器配置中，由主机设备指定的连续逻辑地址被划分为预定大小，并以按顺序重复循环的格式执行写入操作。 。 在双存储器配置中，写入操作以通过F 00，F 10，F 01，F 11重复循环的格式执行。因此，无论连接到控制器的闪存数量如何，控制器处理都是常见的 。

    Memory controller, nonvolatile storage device, nonvolatile storage system, and nonvolatile memory address management method
    14.
    发明授权
    Memory controller, nonvolatile storage device, nonvolatile storage system, and nonvolatile memory address management method 失效
    内存控制器，非易失性存储设备，非易失性存储系统和非易失性存储器地址管理方法

    公开(公告)号：US08051268B2

    公开(公告)日：2011-11-01

    申请号：US11814202

    申请日：2006-07-21

    申请人： Masahiro Nakanishi ,  Tetsushi Kasahara ,  Tomoaki Izumi ,  Kiminori Matsuno ,  Daisuke Kunimune ,  Kazuaki Tamura ,  Yoshiyuki Konishi

    发明人： Masahiro Nakanishi ,  Tetsushi Kasahara ,  Tomoaki Izumi ,  Kiminori Matsuno ,  Daisuke Kunimune ,  Kazuaki Tamura ,  Yoshiyuki Konishi

    IPC分类号： G06F12/00

    CPC分类号： G06F12/0246 ,  G06F2212/1036 ,  G06F2212/7211

    摘要： For address management of a nonvolatile memory, the whole logical address space is divided into logical address ranges (0 to 15), and the physical address space is divided into physical areas (segments (0 to 15)). The logical address ranges are respectively associated with the physical areas (segments) to manage the addresses. The sizes of the logical address ranges are equalized. The size of the physical area (segment (0)) corresponding to the logical address range (0) in which data of high rewrite frequency such as an FAT is expected to be stored is larger than those of the other physical areas, and the logical address ranges and the physical areas are allocated. Alternatively, the sizes of the physical areas are equalized, and the size of the logical address range (0) is set as a smaller one than those of the other logical address ranges. With this, the actual rewrite frequencies of the physical areas (segments) are equal to one another, and consequently the life of the nonvolatile memory can be prolonged.

    摘要翻译： 对于非易失性存储器的地址管理，整个逻辑地址空间被划分为逻辑地址范围（0至15），物理地址空间被划分为物理区域（段（0至15））。 逻辑地址范围分别与物理区域（段）相关联以管理地址。 逻辑地址范围的大小相等。 对应于期望存储诸如FAT的高重写频率的数据的逻辑地址范围（0）的物理区域（段（0））的大小大于其他物理区域的大小，并且逻辑 地址范围和物理区域被分配。 或者，物理区域的大小相等，并且逻辑地址范围（0）的大小被设置为比其他逻辑地址范围的大小小。 由此，物理区域（段）的实际重写频率彼此相等，因此可以延长非易失性存储器的寿命。

    Storage device with buffer control unit
    15.
    发明授权
    Storage device with buffer control unit 有权
    带缓冲控制单元的存储设备

    公开(公告)号：US07818477B2

    公开(公告)日：2010-10-19

    申请号：US11909749

    申请日：2006-03-24

    申请人： Masayuki Toyama ,  Masahiro Nakanishi ,  Tomoaki Izumi ,  Tetsushi Kasahara ,  Kazuaki Tamura ,  Kiminori Matsuno ,  Manabu Inoue

    发明人： Masayuki Toyama ,  Masahiro Nakanishi ,  Tomoaki Izumi ,  Tetsushi Kasahara ,  Kazuaki Tamura ,  Kiminori Matsuno ,  Manabu Inoue

    IPC分类号： G06F3/00 ,  G06F13/00 ,  G06F1/00 ,  G06F11/00

    CPC分类号： G06F3/0659 ,  G06F3/061 ,  G06F3/0656 ,  G06F3/0658 ,  G06F3/0676 ,  G06F11/1441

    摘要： When a control unit (160) in a storage device (100) detects that a write end command or a data amount to be written has been transmitted from a host device (110), the control unit (160) saves control information required for writing data in a control information save memory (142). The control unit (160) also saves data which has not been written in storage medium into a buffer save memory (152) from a data buffer (151) and releases the busy state for the host device (110). The control unit (160) writes the saved data into a storage medium (120). Even if the power is turned OFF before completion of write, write can be performed into the storage medium (120) by using the saved data when the power is turned ON next time.

    摘要翻译： 当存储装置（100）中的控制单元（160）检测到从主机（110）发送写入结束命令或写入数据量时，控制单元（160）保存写入所需的控制信息 控制信息中的数据保存存储器（142）。 控制单元（160）还将从存储介质中未被写入的数据从数据缓冲器（151）保存到缓冲存储器（152）中，并且释放主机设备（110）的忙状态。 控制单元（160）将保存的数据写入存储介质（120）。 即使在完成写入之前电源被关闭，当下一次接通电源时，也可以通过使用保存的数据来对存储介质（120）进行写入。

    Semiconductor memory device, controller, and read/write control method thereof
    17.
    发明授权
    Semiconductor memory device, controller, and read/write control method thereof 有权
    半导体存储器件，控制器及其读/写控制方法

    公开(公告)号：US07203105B2

    公开(公告)日：2007-04-10

    申请号：US10553974

    申请日：2004-10-13

    申请人： Masahiro Nakanishi ,  Tomoaki Izumi ,  Tetsushi Kasahara ,  Kazuaki Tamura ,  Kiminori Matsuno

    发明人： Masahiro Nakanishi ,  Tomoaki Izumi ,  Tetsushi Kasahara ,  Kazuaki Tamura ,  Kiminori Matsuno

    IPC分类号： G11C7/00

    CPC分类号： G06F12/06 ,  G06F2212/2022

    摘要： A controller 102 and four flash memories F0 to F3 are connected by twos to two memory buses, and each flash memory is divided into two regions of substantially the same size to form a first half and a last half regions. In a four-memory configuration, a consecutive logical address specified by a host apparatus is divided into a predetermined size, and a write operation is performed in a format that repeatedly circulates through F0, F1, F2, F3 in this order. In a two-memory configuration, the write operation is performed in a format that repeatedly circulates through F00, F10, F01, F11. Thus, a controller processing is made common regardless of the number of flash memories connected to the controller.

    摘要翻译： 控制器102和四个闪速存储器F 0至F 3通过两个连接到两个存储器总线，并且每个闪速存储器被划分为大致相同大小的两个区域，以形成前半部分和后半个区域。 在四存储器配置中，由主机设备指定的连续逻辑地址被划分为预定大小，并以按顺序重复循环的格式执行写入操作。 。 在双存储器配置中，写入操作以通过F 00，F 10，F 01，F 11重复循环的格式执行。 因此，与控制器连接的闪存数量无关，控制器处理是常见的。

    Memory controller, nonvolatile memory device, nonvolatile memory system and data writing method
    18.
    发明申请
    Memory controller, nonvolatile memory device, nonvolatile memory system and data writing method 有权
    存储控制器，非易失性存储器件，非易失性存储器系统和数据写入方法

    公开(公告)号：US20070011581A1

    公开(公告)日：2007-01-11

    申请号：US11434494

    申请日：2006-05-16

    申请人： Masahiro Nakanishi ,  Manabu Inoue ,  Masayuki Toyama ,  Tomoaki Izumi ,  Tetsushi Kasahara ,  Kazuaki Tamura ,  Kiminori Matsuno

    发明人： Masahiro Nakanishi ,  Manabu Inoue ,  Masayuki Toyama ,  Tomoaki Izumi ,  Tetsushi Kasahara ,  Kazuaki Tamura ,  Kiminori Matsuno

    IPC分类号： G11C29/00

    CPC分类号： G11C29/82 ,  G11C11/5621 ,  G11C16/04 ,  G11C2029/0409

    摘要： With nonvolatile memory device employing a nonvolatile memory such as multiple-valued NAND flash memory or the like in which each memory cell holds data in a plurality of pages, there is such a problem that, if an error occurred under writing data, data stored in other page in the same group of the current page is changed, and hence the object of the present invention is to solve this problem. In writing data into a nonvolatile memory 110, when error occurred under writing data into a certain page, an error page identification part 128 identifies an error type and a physical address of the page where error occurred. An error corrector 129 then corrects errors occurred in other pages belonging to the same group of error occurrence page.

    摘要翻译： 对于采用诸如多值NAND闪速存储器等非易失性存储器的非易失性存储器件，其中每个存储器单元保持多个页面中的数据，存在如下问题：如果在写入数据时发生错误，则存储在 当前页面的同一组中的其他页面被改变，因此本发明的目的是解决这个问题。 在将数据写入非易失性存储器110时，当在特定页面中写入数据时发生错误时，错误页识别部件128识别错误发生的页面的错误类型和物理地址。 错误校正器129然后校正属于同一组错误发生页面的其他页面中发生的错误。

    Semiconductor memory device, memory controller and data recording method
    19.
    发明申请
    Semiconductor memory device, memory controller and data recording method 审中-公开
    半导体存储器件，存储器控制器和数据记录方法

    公开(公告)号：US20050204115A1

    公开(公告)日：2005-09-15

    申请号：US11043411

    申请日：2005-01-27

    申请人： Kiminori Matsuno ,  Masahiro Nakanishi ,  Tomoaki Izumi ,  Tetsushi Kasahara ,  Kazuaki Tamura

    发明人： Kiminori Matsuno ,  Masahiro Nakanishi ,  Tomoaki Izumi ,  Tetsushi Kasahara ,  Kazuaki Tamura

    IPC分类号： G06F12/08

    CPC分类号： G06F12/0246

    摘要： A read/write memory 109 is provided with a memory controller 110 so as to store address management information temporarily. A non-volatile memory access unit 106 writes user data on a non-volatile memory 111 according to a write instruction. When the user data is rewritten, an address management information controller 105 causes a physical block, which is an object to which the address management information 108 is rewritten, to be a to-be-invalid block. After completion of a series of writing process, the to-be-invalid block is turned into an invalid block and the address management information in the read/write memory 109 is rewritten on the non-volatile memory 111.

    摘要翻译： 读/写存储器109设置有存储器控制器110，以临时存储地址管理信息。 非易失性存储器访问单元106根据写入指令将用户数据写入非易失性存储器111。 当用户数据被重写时，地址管理信息控制器105使作为地址管理信息108被重写的对象的物理块成为无效块。 在完成一系列写入处理之后，将无效块变成无效块，并且读/写存储器109中的地址管理信息被重写在非易失性存储器111上。