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公开(公告)号：US20120188811A1
公开(公告)日：2012-07-26
申请号：US13499112
申请日：2010-09-24
IPC分类号： G11C15/00
CPC分类号： G11C15/04
摘要： An associative memory capable of reducing erroneous searches is provided. A storage memory in the associative memory stores reference data. A comparator circuit receives externally applied search data and obtains the distance (for example, the Hamming distance) between the reference data and the search data. An oscillating circuit outputs a pulse signal with an oscillating frequency corresponding to the distance obtained by the comparator circuit. Similarly, the oscillating circuits output pulse signals with oscillating frequencies according to the distance between the reference data in corresponding storage circuits and the search data. A WTA circuit receives the pulse signals. Reference data stored in a storage circuit corresponding to an oscillating circuit that outputs a pulse signal with the highest frequency is determined as the most similar reference data (Winner) to the search data.
摘要翻译： 提供了能够减少错误搜索的关联存储器。 关联存储器中的存储器存储参考数据。 比较器电路接收外部施加的搜索数据，并获得参考数据和搜索数据之间的距离（例如，汉明距离）。 振荡电路输出具有与由比较器电路获得的距离对应的振荡频率的脉冲信号。 类似地，振荡电路根据相应存储电路中的参考数据与搜索数据之间的距离，以振荡频率输出脉冲信号。 WTA电路接收脉冲信号。 存储在与输出具有最高频率的脉冲信号的振荡电路相对应的存储电路中的参考数据被确定为与搜索数据最相似的参考数据（Winner）。
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公开(公告)号：US07860328B2
公开(公告)日：2010-12-28
申请号：US12664946
申请日：2008-07-31
IPC分类号： G06K9/46
摘要： A dividing unit divides respective symbol sequences of input data applied with zigzag scan and a run-length process into a plurality of subsets having similar frequencies of occurrence, depending on a difference in frequencies of occurrence. A table creating unit scans each subset and creates a Huffman coding table for each subset. A coding unit executes a process for performing Huffman coding on each subset by using the Huffman coding table created for the subset, for all of the subsets in the plurality of subsets.
摘要翻译： 分割单元根据发生频率的差异，将施加有锯齿形扫描和游程长度处理的输入数据的各符号序列分割为具有相似发生频率的多个子集。 表创建单元扫描每个子集，并为每个子集创建霍夫曼编码表。 编码单元通过使用针对该子集创建的霍夫曼编码表，对多个子集中的所有子集执行用于对每个子集执行霍夫曼编码的处理。
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公开(公告)号：US20090141531A1
公开(公告)日：2009-06-04
申请号：US12128126
申请日：2008-05-28
IPC分类号： G11C15/04
摘要： Associative memories capable of outputting multiple reference data close to search data are provided. A memory array compares each of the multiple reference data with the search data in parallel and generates multiple comparison current signals representing the result of the comparison. A WLA converts the multiple comparison current signals into voltages. During the first cycle, the WLA detects the lowest voltage among the voltages as Winner and detects the remaining voltages as Loser. After the second cycle, based on feedback signals, the WLA detects all the voltages other than a voltage detected as Winner during the last preceding cycle, and detects the lowest voltage among the detected voltages as Winner and detects the remaining detected voltages as Loser. The WLA repeats these operations k times.
摘要翻译： 提供能够输出接近搜索数据的多个参考数据的关联存储器。 存储器阵列并行地将多个参考数据与搜索数据进行比较，并且生成表示比较结果的多个比较电流信号。 WLA将多个比较电流信号转换为电压。 在第一个周期内，WLA将电压中的最低电压检测为Winner，并检测剩余电压为失败者。 在第二周期之后，WLA根据反馈信号，检测在上一周期内被检测为Winner的电压之外的所有电压，并检测检测到的电压中的最低电压为Winner，并检测剩余的检测电压为失败者。 WLA重复这些操作k次。
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14.发明授权公开(公告)号：US07526127B2
公开(公告)日：2009-04-28
申请号：US10915559
申请日：2004-08-11
IPC分类号： G06K9/34
CPC分类号： G06K9/342 , G06K9/00986 , G06T7/11 , G06T7/20 , G06T2200/28 , G06T2207/10016
摘要： In a boundary active only scheme proposed by the present invention, only a cell in a boundary of region growth is brought into an active mode, and the other cells are brought into a standby mode. The respective cells perform state transition in parallel, and decision of the state transition performed for each clock cycle is not performed in a case where any of the three conditions that none of the adjacent cells is ignited, the cell itself is already ignited, and the cell already belongs to a certain divided region is satisfied. Therefore the number of simultaneously operating cells and that of coupling weight registers are minimized, and control is automatically executed to reduce power consumption.
摘要翻译： 在本发明提出的仅边界有效方案中，只有区域增长边界中的单元才能进入活动模式，其他单元进入待机模式。 各个小区并行执行状态转换，并且在没有相邻小区被点燃的三个条件，小区本身已被点燃的情况下，不执行对于每个时钟周期执行的状态转换的判定，并且 细胞已经属于某个分割区域。 因此，同时工作的单元和耦合重量寄存器的数量最小化，自动执行控制以降低功耗。
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公开(公告)号：US07117291B2
公开(公告)日：2006-10-03
申请号：US10787240
申请日：2004-02-27
申请人： Hans Jurgen Mattausch , Tetsushi Koide , Tetsuo Hironaka , Hiroshi Uchida , Koh Johguchi , Zhaomin Zhu
发明人： Hans Jurgen Mattausch , Tetsushi Koide , Tetsuo Hironaka , Hiroshi Uchida , Koh Johguchi , Zhaomin Zhu
CPC分类号： G11C8/12
摘要： In a synchronous multi-port bank memory, registers/buffers receive a read/write signal and an address signal from each of external ports, receive and send a data signal to and from each of the external ports, and receive and send a port block signal. An access conflict management circuit receives the address signals from the registers and buffers and generates the port block signal when an access conflict to the bank occurs. A switching network receives the read/write signal and the address signal from the registers/buffers and generates a bank selection signal when no port block signal is received, so as to activate the selected bank. Thus, memory access cycle time is shortened. A synchronous 1-port bank memory is also constructed similarly.
摘要翻译： 在同步多端口组存储器中，寄存器/缓冲器从每个外部端口接收读/写信号和地址信号，从每个外部端口接收和发送数据信号，并接收和发送端口块 信号。 访问冲突管理电路从寄存器和缓冲器接收地址信号，并且当发生对存储体的访问冲突时产生端口块信号。 开关网络从寄存器/缓冲器接收读/写信号和地址信号，并且当没有接收到端口阻塞信号时产生存储体选择信号，以激活所选择的存储体。 因此，存储器访问周期时间缩短。 类似地构造同步1端口组存储器。
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公开(公告)号：US08587980B2
公开(公告)日：2013-11-19
申请号：US13499112
申请日：2010-09-24
IPC分类号： G11C15/00
CPC分类号： G11C15/04
摘要： An associative memory capable of reducing erroneous searches is provided. A storage memory in the associative memory stores reference data. A comparator circuit receives externally applied search data and obtains the distance (for example, the Hamming distance) between the reference data and the search data. An oscillating circuit outputs a pulse signal with an oscillating frequency corresponding to the distance obtained by the comparator circuit. Similarly, the oscillating circuits output pulse signals with oscillating frequencies according to the distance between the reference data in corresponding storage circuits and the search data. A WTA circuit receives the pulse signals. Reference data stored in a storage circuit corresponding to an oscillating circuit that outputs a pulse signal with the highest frequency is determined as the most similar reference data (Winner) to the search data.
摘要翻译： 提供了能够减少错误搜索的关联存储器。 关联存储器中的存储器存储参考数据。 比较器电路接收外部施加的搜索数据，并获得参考数据和搜索数据之间的距离（例如，汉明距离）。 振荡电路输出具有与由比较器电路获得的距离对应的振荡频率的脉冲信号。 类似地，振荡电路根据相应存储电路中的参考数据与搜索数据之间的距离，以振荡频率输出脉冲信号。 WTA电路接收脉冲信号。 存储在与输出具有最高频率的脉冲信号的振荡电路相对应的存储电路中的参考数据被确定为与搜索数据最相似的参考数据（Winner）。
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公开(公告)号：US07957171B2
公开(公告)日：2011-06-07
申请号：US12128126
申请日：2008-05-28
IPC分类号： G11C15/00
摘要： Associative memories capable of outputting multiple reference data close to search data are provided. A memory array compares each of the multiple reference data with the search data in parallel and generates multiple comparison current signals representing the result of the comparison. A WLA converts the multiple comparison current signals into voltages. During the first cycle, the WLA detects the lowest voltage among the voltages as Winner and detects the remaining voltages as Loser. After the second cycle, based on feedback signals, the WLA detects all the voltages other than a voltage detected as Winner during the last preceding cycle, and detects the lowest voltage among the detected voltages as Winner and detects the remaining detected voltages as Loser. The WLA repeats these operations k times.
摘要翻译： 提供能够输出接近搜索数据的多个参考数据的关联存储器。 存储器阵列并行地将多个参考数据与搜索数据进行比较，并且生成表示比较结果的多个比较电流信号。 WLA将多个比较电流信号转换为电压。 在第一个周期内，WLA将电压中的最低电压检测为Winner，并检测剩余电压为失败者。 在第二周期之后，WLA根据反馈信号，检测在上一周期内被检测为Winner的电压之外的所有电压，并检测检测到的电压中的最低电压为Winner，并检测剩余的检测电压为失败者。 WLA重复这些操作k次。
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公开(公告)号：US07853075B2
公开(公告)日：2010-12-14
申请号：US12601595
申请日：2008-07-31
CPC分类号： G06T7/11 , G06T2207/10024
摘要： A pixel-value detecting circuit (1) detects RGB values of each pixel of an input image and outputs the detected RGB values to a connection weight determining circuit (2). When both of two adjacent pixels have achromatic color, the connection weight determining circuit (2) determines a first connection weight, which is a connection weight between the two pixels, by using only the RGB values. When one of the two pixels has achromatic color, the connection weight determining circuit (2) determines, as a connection weight, a second connection weight that is smaller than the first connection weight, by using the RGB values and saturations. When both of the two pixels have chromatic color, the connection weight determining circuit (2) determines, as a connection weight, a third connection weight that is greater than or equal to the first connection weight, by using the RGB values and hues. An image segmenting circuit (3) segments the input image into images of subjects by using the connection weight determined by the connection weight determining circuit (2).
摘要翻译： 像素值检测电路（1）检测输入图像的每个像素的RGB值，并将检测到的RGB值输出到连接权重确定电路（2）。 当两个相邻像素都具有无彩色时，连接权重确定电路（2）仅通过使用RGB值来确定作为两个像素之间的连接权重的第一连接权重。 当两个像素之一具有无彩色时，连接权重确定电路（2）通过使用RGB值和饱和度来确定小于第一连接权重的第二连接权重作为连接权重。 当两个像素都具有彩色时，连接权重确定电路（2）通过使用RGB值和色调来确定作为连接权重的大于或等于第一连接权重的第三连接权重。 图像分割电路（3）通过使用由连接权重确定电路（2）确定的连接权重将输入图像分割成被摄体的图像。
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19.发明申请OFFSET REMOVAL CIRCUIT, ASSOCIATIVE MEMORY INCLUDING THE SAME, AND OFFSET VOLTAGE REMOVAL METHOD 有权偏移电路，包括相同的相关存储器和偏移电压去除方法公开(公告)号：US20100202178A1
公开(公告)日：2010-08-12
申请号：US12665316
申请日：2008-07-31
CPC分类号： H03F3/45475 , G11C15/00 , H03F3/45968 , H03F2203/45136 , H03F2203/45212 , H03F2203/45588
摘要： An offset removal circuit (10) includes a removal circuit (1) and a removal circuit (2). The removal circuit (1) digitally removes offset voltage from an input voltage Vin. The removal circuit (2) removes offset voltage, in an analog manner, from the voltage subjected to offset voltage removal by the removal circuit (1). Then, the removal circuit (2) outputs the voltage subjected to the offset voltage removal to a non-inverting input terminal of a differential amplifier (20).
摘要翻译： 偏移消除电路（10）包括去除电路（1）和去除电路（2）。 去除电路（1）从输入电压Vin数字地去除偏移电压。 去除电路（2）以模拟方式去除由去除电路（1）去除偏移电压的电压的偏移电压。 然后，去除电路（2）将经过偏移电压去除的电压输出到差分放大器（20）的非反相输入端子。
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公开(公告)号：US20100179976A1
公开(公告)日：2010-07-15
申请号：US12687756
申请日：2010-01-14
申请人： Masakatsu ISHIZAKI , Takeshi Kumaki , Masaharu Tagami , Yuta Imai , Tetsushi Koide , Hans Jürgen Mattausch , Takayuki Gyoten , Hideyuki Noda , Yoshihiro Okuno , Kazutami Arimoto
发明人： Masakatsu ISHIZAKI , Takeshi Kumaki , Masaharu Tagami , Yuta Imai , Tetsushi Koide , Hans Jürgen Mattausch , Takayuki Gyoten , Hideyuki Noda , Yoshihiro Okuno , Kazutami Arimoto
CPC分类号： G06F7/5235 , G06F7/5324 , G06F7/5338
摘要： A semiconductor device includes a decoder receiving first multiplier data of 3 bits indicating a multiplier to output a shift flag, an inversion flag, and an operation flag in accordance with Booth's algorithm, and a first partial product calculation unit receiving first multiplicand data of 2 bits indicating a multiplicand, a shift flag, an inversion flag, and an operation flag to select one of the higher order bit and lower order bit of the first multiplicand data based on the shift flag, invert or non-invert the selected bit based on the inversion flag, select one of the inverted or non-inverted data and data of a predetermined logic level based on the operation flag, and output the selected data as partial product data indicating the partial product of the first multiplier data and the first multiplicand data.
摘要翻译： 半导体器件包括：解码器，接收根据布斯（Booth）算法的3比特的第一乘法器数据，指示乘法器输出移位标志，反转标志和操作标志，第一部分乘积计算单元接收2位的第一被乘数数据 指示被乘数，移位标志，反转标志和操作标志，以基于移位标志来选择第一被乘数数据的高位位和低位位之一，基于该选择位反转或非反转所选位 反转标志，基于操作标志选择反相或非反相数据和预定逻辑电平的数据之一，并将选择的数据作为指示第一乘法器数据和第一被乘数数据的部分乘积的部分乘积数据输出。
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