公开(公告)号：US06392918B2

公开(公告)日：2002-05-21

申请号：US09817578

申请日：2001-03-26

申请人： Georg Braun ,  Heinz Hönigschmid ,  Kurt Hoffmann ,  Oskar Kowarik ,  Thomas Röhr

发明人： Georg Braun ,  Heinz Hönigschmid ,  Kurt Hoffmann ,  Oskar Kowarik ,  Thomas Röhr

IPC分类号： G11C1122

CPC分类号： G11C11/22

摘要： A circuit for generating a reference voltage for the reading out from and the evaluation of read output signals which are read out with a constant plate voltage from storage cells of a ferroelectric memory via bit lines. In the circuit, a reference voltage device is formed of two reference cells that are subjected to the action of complementary signals. The reference cells can be simultaneously read out in order to generate the reference voltage in a selection and evaluation device.

摘要翻译： 用于产生用于读出的参考电压的电路和用于经由位线从铁电存储器的存储单元以恒定板电压读出的读取输出信号的评估。 在该电路中，参考电压装置由经受互补信号的作用的两个参考单元形成。 可以同时读出参考单元，以便在选择和评估装置中产生参考电压。

公开(公告)号：US06445607B2

公开(公告)日：2002-09-03

申请号：US09829288

申请日：2001-04-09

申请人： Robert Esterl ,  Heinz Hönigschmid ,  Helmut Kandolf ,  Thomas Röhr

发明人： Robert Esterl ,  Heinz Hönigschmid ,  Helmut Kandolf ,  Thomas Röhr

IPC分类号： G11C1122

CPC分类号： G11C11/22

摘要： A description is given of a method for operating an integrated memory which has memory cells each having a selection transistor and a storage capacitor with a ferroelectric storage effect. The memory contains a plate line, which is connected to one of the column lines via a series circuit containing a selection transistor and a storage capacitor of respective memory cells. A memory access is carried out according to the “pulsed plate concept”. In this case, the temporal sequence is controlled in such a way that, in an access cycle, the storage capacitor of the memory cell to be selected is in each case charged and discharged by the same amount. An attenuation or destruction of the information stored in the memory cells, which is caused by source-drain leakage currents of unactivated selection transistors, is thus avoided.

摘要翻译： 给出了一种用于操作具有存储单元的集成存储器的方法，每个存储单元都具有选择晶体管和具有铁电存储效应的存储电容器。 存储器包含板线，其经由包含各个存储器单元的选择晶体管和存储电容器的串联电路连接到列线之一。 根据“脉冲板概念”进行记忆存取。 在这种情况下，以这样的方式控制时间序列，使得在访问周期中，要选择的存储单元的存储电容器在每种情况下都以相同的量被放电。 因此避免了由未激活的选择晶体管的源漏泄漏电流引起的存储在存储单元中的信息的衰减或破坏。

公开(公告)号：US06664158B2

公开(公告)日：2003-12-16

申请号：US10034931

申请日：2001-11-21

申请人： Christine Dehm ,  Heinz Hönigschmid ,  Thomas Röhr

发明人： Christine Dehm ,  Heinz Hönigschmid ,  Thomas Röhr

IPC分类号： H01L218242

CPC分类号： H01L27/11502 ,  H01L27/11507

摘要： An integrated ferroelectric memory configuration and a method for producing the integrated ferroelectric memory configuration, in which memory cells are arranged using the stacking principle, and both capacitor electrodes, which are located one above the other, of each memory cell are directly electrically connected by means of contact plugs to corresponding source and drain regions of an associated selection transistor in the substrate. Contact plugs for the contact connection to the upper capacitor electrodes are produced from above the configuration.

公开(公告)号：US06826075B2

公开(公告)日：2004-11-30

申请号：US09905853

申请日：2001-07-13

申请人： Dietmar Gogl ,  Thomas Röhr ,  Heinz Hönigschmid

发明人： Dietmar Gogl ,  Thomas Röhr ,  Heinz Hönigschmid

IPC分类号： G11C506

CPC分类号： G11C11/16 ,  G11C7/18 ,  H01L27/222

摘要： A memory matrix has at least one cell array including column lines and row lines. Memory elements are situated at points where the row lines and column lines intersect one another. In each case two adjacent lines are guided such that they cross one another in such a way that the two lines change their spatial configurations in sections along the direction in which they run. Thus an overcoupling of signals between the lines is minimized.

摘要翻译： 存储器矩阵具有至少一个包括列线和行线的单元阵列。 存储元件位于行线和列线彼此相交的点处。 在每种情况下，两个相邻的线被引导使得它们彼此交叉，使得两条线沿着它们运行的​​方向在其部分中改变它们的空间构造。 因此，线路之间的信号过度耦合被最小化。

公开(公告)号：US06645809B2

公开(公告)日：2003-11-11

申请号：US09995209

申请日：2001-11-27

申请人： Heinz Hönigschmid ,  Thomas Röhr

发明人： Heinz Hönigschmid ,  Thomas Röhr

IPC分类号： H01L218242

CPC分类号： H01L27/11502 ,  G11C11/22 ,  H01L27/101 ,  H01L27/11507

摘要： In order to provide a particularly space-saving capacitor configuration in a memory device, a plurality of second electrode regions which are not in direct electrical contact with one another are formed on areas of a first electrode region covered by a dielectric material. During operation of the capacitor configuration, portions of the first electrode region form bottom electrodes which are connected by a connecting region, so that an additional connecting device for the bottom electrodes is not necessary.

公开(公告)号：US06538913B2

公开(公告)日：2003-03-25

申请号：US09826232

申请日：2001-04-04

申请人： Heinz Hönigschmid ,  Thomas Röhr

发明人： Heinz Hönigschmid ,  Thomas Röhr

IPC分类号： G11C1122

CPC分类号： G11C11/22

摘要： The invention relates to a method for operating a ferroelectric memory configuration in the VDD/2 mode. The memory configuration has a large number of memory cells which each have at least one selection transistor, one storage capacitor with an upper and a lower electrode and one short-circuiting transistor whose source-drain junction is connected in parallel with the storage capacitor. After a read or write procedure in which the memory cells are driven via respectively associated word lines and via respectively associated bit lines which are precharged in a precharge phase, the short-circuiting transistor is driven during a standby phase and in the process short-circuits the electrodes in the storage capacitor. The method is characterized in that the time of the standby phase coincides with the time of the precharge phase and, in the process, the bit lines are at a different potential with respect to that of the two electrodes of the storage capacitor.

摘要翻译： 本发明涉及一种在VDD / 2模式下操作铁电存储器配置的方法。 存储器配置具有大量存储单元，每个存储单元具有至少一个选择晶体管，一个具有上下电极的存储电容器和一个源极 - 漏极结与存储电容器并联连接的短路晶体管。 在通过分别关联的字线驱动存储单元并通过在预充电阶段中预充电的分别相关联的位线的读或写过程之后，短路晶体管在待机阶段被驱动，并且在过程中短路 存储电容器中的电极。 该方法的特征在于，待机阶段的时间与预充电阶段的时间一致，并且在该过程中，位线相对于存储电容器的两个电极的位线处于不同的电位。

公开(公告)号：US06515890B2

公开(公告)日：2003-02-04

申请号：US09780305

申请日：2001-02-09

申请人： Robert Esterl ,  Helmut Kandolf ,  Heinz Hönigschmid ,  Thomas Röhr

发明人： Robert Esterl ,  Helmut Kandolf ,  Heinz Hönigschmid ,  Thomas Röhr

IPC分类号： G11C1122

CPC分类号： G11C11/22

摘要： An integrated semiconductor memory has memory cells with a ferroelectric memory property. The memory cells are in each case connected between a column line and a charge line. The column line is connected to a read amplifier which supplies an output signal. The charge line is connected to a driver circuit which provides the charge line with a given potential. In an inactive mode, the column line and the charge line are jointly connected to a connection for a common supply potential in the read amplifier or in the driver circuit. As a result, a relatively quick equalization of a potential between the lines is possible. Thus, unintended changes in the memory cell content due to interfering voltages are avoided.

摘要翻译： 集成半导体存储器具有具有铁电存储器特性的存储单元。 存储器单元在每种情况下都连接在列线和充电线之间。 列线连接到提供输出信号的读取放大器。 充电线连接到向给定电位提供充电线的驱动器电路。 在非活动模式下，列线和充电线在读取放大器或驱动电路中共同连接到用于共同供电电位的连接。 结果，线之间的电位的相对快速的均衡是可能的。 因此，避免了由于干扰电压引起的存储器单元内容的意外变化。

公开(公告)号：US06483768B2

公开(公告)日：2002-11-19

申请号：US09898221

申请日：2001-07-03

申请人： Thomas Böhm ,  Dietmar Gogl ,  Gerhard Müller ,  Thomas Röhr

发明人： Thomas Böhm ,  Dietmar Gogl ,  Gerhard Müller ,  Thomas Röhr

IPC分类号： G11C800

CPC分类号： G11C11/16 ,  G11C7/12

摘要： A current driver configuration for MRAMs includes word-line drivers and bit-line drivers at respective first ends of word lines and bit lines. The word line drivers and the bit line drivers each include a series circuit formed by an n-channel field-effect transistor and a current source. Further series circuits are provided at the respective second ends of the word lines and the bit lines. Each of the further series circuits includes a second n-channel field-effect transistor and a voltage source.

摘要翻译： MRAM的当前驱动器配置包括在字线和位线的相应第一端处的字线驱动器和位线驱动器。 字线驱动器和位线驱动器各自包括由n沟道场效应晶体管和电流源形成的串联电路。 在字线和位线的各自的第二端设置有更多的串联电路。 每个其它串联电路包括第二n沟道场效应晶体管和电压源。

公开(公告)号：US06259641B1

公开(公告)日：2001-07-10

申请号：US09560545

申请日：2000-04-28

申请人： Zoltan Manyoki ,  Thomas Röhr ,  Thomas Böhm

发明人： Zoltan Manyoki ,  Thomas Röhr ,  Thomas Böhm

IPC分类号： G11C700

CPC分类号： G11C11/22 ,  G11C7/06 ,  G11C7/1042

摘要： An integrated memory includes a cell array having memory cells disposed at points of intersection of first bit lines and second bit lines with word lines in the cell array. When one of the memory cells is addressed, the memory content is not affected if respective bit lines associated with each of the memory cells are at a standby potential. Sense amplifiers for amplifying data read from the memory cells onto the bit lines are included, each associated with respective first and second bit lines and disposed on opposite sides of the cell array. Also provided are first switching elements, through which each bit line is connected to the associated sense amplifier, and second switching elements, through which each bit line is connected, on that side of its first switching element which is remote from the associated sense amplifier, to a standby potential. Column selection lines are each connected to the control connections of the first and second switching elements in at least one of the first and one of the second bit lines. Each bit line is connected to the standby potential through third switching elements. A first control line is connected to all the third switching elements in the first bit lines, and a second control line is connected to all the third switching elements in the second bit lines.

摘要翻译： 集成存储器包括具有存储单元阵列的单元阵列，该存储单元设置在第一位线和第二位线的交点处与单元阵列中的字线。 当存储器单元之一被寻址时，如果与每个存储器单元相关联的各个位线处于待机电位，则存储器内容不受影响。 包括用于将从存储器单元读取的数据放大到位线的读出放大器，每个与相应的第一和第二位线相关联并且设置在单元阵列的相对侧上。 还提供了第一开关元件，每个位线通过该开关元件连接到相关联的读出放大器，以及在其第一开关元件的远离相关读出放大器的该侧上连接每个位线的第二开关元件， 到备用电位。 列选择线各自连接到第一和第二位线中的至少一个中的第一和第二开关元件的控制连接。 每个位线通过第三个开关元件连接到待机电位。 第一控制线连接到第一位线中的所有第三开关元件，第二控制线连接到第二位线中的所有第三开关元件。

公开(公告)号：US07158405B2

公开(公告)日：2007-01-02

申请号：US10190812

申请日：2002-07-08

申请人： Thomas Böhm ,  Stefan Lammers ,  Thomas Röhr

发明人： Thomas Böhm ,  Stefan Lammers ,  Thomas Röhr

IPC分类号： G11C11/00

CPC分类号： G11C11/16 ,  G11C8/12

摘要： A semiconductor memory device has a particularly space-saving configuration of the memory areas and, in particular, of the selection devices assigned to the memory areas. During operation, each selection device can be assigned in a controllable manner to a plurality of memory areas such that selectively each of the selection devices can carry out an addressing and selection in one of the assigned memory areas.

摘要翻译： 半导体存储器件具有特别节省空间的存储区域配置，特别是分配给存储区域的选择设备。 在操作期间，可以以可控的方式将每个选择装置分配给多个存储区域，使得选择性地每个选择装置可以在分配的存储区域之一中执行寻址和选择。