公开(公告)号：US20230234188A1

公开(公告)日：2023-07-27

申请号：US17727279

申请日：2022-04-22

Applicant: Tokyo Electron Limited

Inventor： Nathan Ip ,  Nima Nejadsadeghi

IPC: B25B11/00 ,  H01L21/683 ,  H01L21/66

CPC classification number: B25B11/005 ,  H01L21/6838 ,  H01L22/20

Abstract: A wafer bonding apparatus including: a first chuck in a processing chamber, the first chuck being configured to hold a first wafer, the first chuck including: a chuck body, and a tunable stiffness layer including a plurality of actuators, the plurality of actuators including a tunable stiffness material, the tunable stiffness layer being disposed below the chuck body; a controller configured to send control signals to one or more of the plurality of actuators; and a vacuum line on the chuck body configured to apply a vacuum pressure from a vacuum pump to the first wafer; and a second chuck in the processing chamber, the second chuck being configured to hold a second wafer to be bonded with the first wafer; and where a stiffness of the plurality of actuators is configured to change based on the control signals from the controller.

公开(公告)号：US20230102438A1

公开(公告)日：2023-03-30

申请号：US17484204

申请日：2021-09-24

Applicant: Tokyo Electron Limited

Inventor： Nathan Ip ,  Megan Wooley

IPC: G05B19/418 ,  G06F30/31

Abstract: Sensitivity calculations are provided of a process model through the rate of change of a model fingerprint with respect to process variables and defects. A fingerprint sensitivity table is generated, where process variables are associated with a set of fingerprint sensitivities. The fingerprint of incoming substrates is monitored through a production process by applying the same fingerprint method that is used in the process model. Calculations are made of the difference between the incoming substrate fingerprint and the process model predicted fingerprint. This difference fingerprint is compared against the table of fingerprint sensitivities to find the process variable most likely to be responsible for the difference. Spatial relationships between process variables and actual measurements on the substrate may be obtained. Correlation through fingerprint sensitivity improves the ability to pinpoint faulty process tools. The difference fingerprint may also identify the formation of defects on a substrate.

公开(公告)号：US11594431B2

公开(公告)日：2023-02-28

申请号：US17236785

申请日：2021-04-21

Applicant: Tokyo Electron Limited

Inventor： Nathan Ip

IPC: H01L21/67

Abstract: Various embodiments of wafer bonding apparatuses and methods are described herein for reducing distortion in a post-bonded wafer pair. More specifically, the present disclosure provides embodiments of wafer bonding apparatuses and methods to reduce post-bond wafer distortion that occurs primarily within the center and/or the edge of the post-bonded wafer pair. In the present disclosure, post-bonded wafer distortion is reduced by correcting for variations in the pre-bond wafer shapes. Variations in pre-bond wafer shape are corrected, or compensated for, by making hardware modifications to the wafer chuck. Such modifications may include, but are not limited to, modifications to the surface height and/or the temperature of the wafer chuck. Although hardware modifications are disclosed herein for reducing post-bond wafer distortion near the center and/or the edge of the post-bonded wafer pair, similar modifications can be made to reduce post-bond wafer distortion within other areas or zones of the post-bonded wafer pair.

公开(公告)号：US11335607B2

公开(公告)日：2022-05-17

申请号：US16924847

申请日：2020-07-09

Applicant: Tokyo Electron Limited

Inventor： Nathan Ip

IPC: G11C16/04 ,  H01L21/66 ,  H01L23/00 ,  H01L21/18 ,  G06F30/27

Abstract: A method includes having a first wafer bonding recipe and a model of a wafer bonding process, the model comprising an input indicative of a physical parameter of a first wafer to be bonded to a second wafer and configured to output a wafer bonding recipe based on the physical parameter of the first wafer; obtaining measurements of the first wafer to obtain the physical parameter of the first wafer; generating, by the model, the first wafer bonding recipe based on the physical parameter of the first wafer; and bonding the first wafer to the second wafer in accordance with the first wafer bonding recipe to produce a first post-bond wafer.

公开(公告)号：US11244873B2

公开(公告)日：2022-02-08

申请号：US16666087

申请日：2019-10-28

Applicant: Tokyo Electron Limited

Inventor： Carlos A. Fonseca ,  Nathan Ip

IPC: H01L21/66 ,  B81C1/00

Abstract: In one embodiment, a method includes obtaining wafer measurements of a characteristic of a semiconductor wafer at each of a plurality of process steps during a semiconductor wafer fabrication process, where each of the wafer measurements is associated with a spatial location on the semiconductor wafer from which the measurement is obtained. The method may further include creating a process step fingerprint from the obtained wafer measurements for each process step. The method may further include correlating the process step fingerprint of one of the plurality of process steps to the process step fingerprint of another one of the plurality of process steps to produce a transfer function.