公开(公告)号：US20190139798A1

公开(公告)日：2019-05-09

申请号：US16179492

申请日：2018-11-02

Applicant: Tokyo Electron Limited

Inventor： Carlos A. Fonseca ,  Nathan Ip ,  Joel Estrella

IPC: H01L21/67 ,  H01L21/66

Abstract: Described herein are techniques related to a semiconductor fabrication process that facilitates the enhancement of systemic conformities of patterns of the fabricated semiconductor wafer. A semiconductor wafer with maximized systemic conformities of patterns will maximize the electrical properties and/or functionality of the electronic devices formed as part of the fabricated semiconductor wafer. This Abstract is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims.

公开(公告)号：US20160141169A1

公开(公告)日：2016-05-19

申请号：US15006965

申请日：2016-01-26

Applicant: Tokyo Electron Limited

Inventor： Carlos A. Fonseca ,  Benjamen M. Rathsack ,  Jeffrey Smith ,  Anton J. deVilliers ,  Lior Huli

IPC: H01L21/02 ,  H01L21/66 ,  H01L21/687

CPC classification number: H01L21/02016 ,  G03F7/70783 ,  H01L21/30625 ,  H01L21/687 ,  H01L22/12 ,  H01L22/20

Abstract: Embodiments described relate to a method and apparatus for reducing lithographic distortion. A backside of a semiconductor substrate may be texturized. Then a lithographic process may be performed on the semiconductor substrate having the texturized backside.

公开(公告)号：US11244873B2

公开(公告)日：2022-02-08

申请号：US16666087

申请日：2019-10-28

Applicant: Tokyo Electron Limited

Inventor： Carlos A. Fonseca ,  Nathan Ip

IPC: H01L21/66 ,  B81C1/00

Abstract: In one embodiment, a method includes obtaining wafer measurements of a characteristic of a semiconductor wafer at each of a plurality of process steps during a semiconductor wafer fabrication process, where each of the wafer measurements is associated with a spatial location on the semiconductor wafer from which the measurement is obtained. The method may further include creating a process step fingerprint from the obtained wafer measurements for each process step. The method may further include correlating the process step fingerprint of one of the plurality of process steps to the process step fingerprint of another one of the plurality of process steps to produce a transfer function.

公开(公告)号：US09711419B2

公开(公告)日：2017-07-18

申请号：US14833044

申请日：2015-08-22

Applicant: Tokyo Electron Limited

Inventor： Carlos A. Fonseca ,  Benjamen M. Rathsack ,  Jeffrey Smith ,  Anton J. deVilliers ,  Lior Huli ,  Teruhiko Kodama ,  Joshua S. Hooge

IPC: H01B13/00 ,  H01L21/66 ,  H01L21/306 ,  G03F7/20 ,  H01L21/027

CPC classification number: H01L22/12 ,  G03F7/70783 ,  H01L21/0274 ,  H01L21/30625 ,  H01L22/20

Abstract: Embodiments described relate to a method and apparatus for reducing lithographic distortion. A backside of a semiconductor substrate may be texturized. Then a lithographic process may be performed on the semiconductor substrate having the texturized backside.

公开(公告)号：US20160043007A1

公开(公告)日：2016-02-11

申请号：US14833044

申请日：2015-08-22

Applicant: Tokyo Electron Limited

Inventor： Carlos A. Fonseca ,  Benjamen M. Rathsack ,  Jeffrey Smith ,  Anton J. deVilliers ,  Lior Huli ,  Teruhiko Kodama ,  Joshua S. Hooge

IPC: H01L21/66 ,  H01L21/306 ,  H01L21/268

CPC classification number: H01L22/12 ,  G03F7/70783 ,  H01L21/0274 ,  H01L21/30625 ,  H01L22/20

Abstract: Embodiments described relate to a method and apparatus for reducing lithographic distortion. A backside of a semiconductor substrate may be texturized. Then a lithographic process may be performed on the semiconductor substrate having the texturized backside.

公开(公告)号：US11435393B2

公开(公告)日：2022-09-06

申请号：US16179526

申请日：2018-11-02

Applicant: Tokyo Electron Limited

Inventor： Carlos A. Fonseca ,  Nathan Ip ,  Joel Estrella

IPC: G01R31/28 ,  G01R1/02 ,  G06F30/30 ,  H01L21/67 ,  H01L21/66 ,  G06F119/18

Abstract: Described herein are techniques related to a semiconductor fabrication process that facilitates the enhancement of systemic conformities of patterns of the fabricated semiconductor wafer. A semiconductor wafer with maximized systemic conformities of patterns will maximize the electrical properties and/or functionality of the electronic devices formed as part of the fabricated semiconductor wafer. This Abstract is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims.

公开(公告)号：US11346882B2

公开(公告)日：2022-05-31

申请号：US16179492

申请日：2018-11-02

Applicant: Tokyo Electron Limited

Inventor： Carlos A. Fonseca ,  Nathan Ip ,  Joel Estrella

IPC: G01R31/28 ,  H01L21/67 ,  H01L21/66 ,  G01R1/02 ,  G06F30/30 ,  G06F119/18

Abstract: Described herein are techniques related to a semiconductor fabrication process that facilitates the enhancement of systemic conformities of patterns of the fabricated semiconductor wafer. A semiconductor wafer with maximized systemic conformities of patterns will maximize the electrical properties and/or functionality of the electronic devices formed as part of the fabricated semiconductor wafer. This Abstract is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims.

公开(公告)号：US20190137565A1

公开(公告)日：2019-05-09

申请号：US16179526

申请日：2018-11-02

Applicant: Tokyo Electron Limited

Inventor： Carlos A. Fonseca ,  Nathan Ip ,  Joel Estrella

IPC: G01R31/28 ,  G06F17/50 ,  G01R1/02

Abstract: Described herein are techniques related to a semiconductor fabrication process that facilitates the enhancement of systemic conformities of patterns of the fabricated semiconductor wafer. A semiconductor wafer with maximized systemic conformities of patterns will maximize the electrical properties and/or functionality of the electronic devices formed as part of the fabricated semiconductor wafer. This Abstract is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims.