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公开(公告)号:US20210020769A1
公开(公告)日:2021-01-21
申请号:US16525513
申请日:2019-07-29
Applicant: UNITED MICROELECTRONICS CORP.
Inventor: Kuo-Hsing Lee , Yi-Chung Sheng , Sheng-Yuan Hsueh , Chih-Kai Kang , Guan-Kai Huang , Chien-Liang Wu
IPC: H01L29/778 , H01L29/66
Abstract: A high electron mobility transistor (HEMT) includes a carrier transit layer, a carrier supply layer, a main gate, a control gate, a source electrode and a drain electrode. The carrier transit layer is on a substrate. The carrier supply layer is on the carrier transit layer. The main gate and the control gate are on the carrier supply layer. The source electrode and the drain electrode are at two opposite sides of the main gate and the control gate, wherein the source electrode is electrically connected to the control gate by a metal interconnect. The present invention also provides a method of forming a high electron mobility transistor (HEMT).
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公开(公告)号:US10777508B2
公开(公告)日:2020-09-15
申请号:US15347757
申请日:2016-11-09
Applicant: UNITED MICROELECTRONICS CORP.
Inventor: Chih-Kai Kang , Sheng-Yuan Hsueh , Yi-Chung Sheng , Kuo-Yu Liao , Shu-Hung Yu , Hung-Hsu Lin , Hsiang-Hung Peng
IPC: H01L23/544 , H01L27/092 , H01L27/02 , G03F9/00 , H01L21/8238
Abstract: A semiconductor device includes a substrate including a plurality of chip areas and a scribe line defined thereon, and a mark pattern disposed in the scribe line. The mark pattern includes a plurality of unit cells immediately adjacent to each other, and each unit cell includes a first active region, a second active region isolated from the first active region, a plurality of first gate structures extending along a first direction and arranged along a second direction perpendicular to the first direction, and a plurality of first conductive structures. The first gate structures straddle the first active region and the second active region. The first conductive structures are disposed on the first active region, the second active region, and two opposite sides of the first gate structures.
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公开(公告)号:US10002864B1
公开(公告)日:2018-06-19
申请号:US15365906
申请日:2016-11-30
Applicant: UNITED MICROELECTRONICS CORP.
Inventor: Hsin-Hsien Chen , Sheng-Yuan Hsueh , Yi-Chung Sheng , Chih-Kai Kang , Wen-Kai Lin , Shu-Hung Yu
IPC: H01L29/06 , H01L27/06 , H01L49/02 , H01L23/528 , H01L21/768
Abstract: An intra-metal capacitor is provided. The intra-metal capacitor is formed in a dielectric layer and comprising a first electrode and a second electrode, wherein the first electrode penetrate through the whole thickness of the dielectric layer, and the second electrode does not penetrate through the whole thickness of the dielectric layer.
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公开(公告)号:US20250071983A1
公开(公告)日:2025-02-27
申请号:US18372130
申请日:2023-09-24
Applicant: UNITED MICROELECTRONICS CORP.
Inventor: Kuo-Hsing Lee , Sheng-Yuan Hsueh , Yung-Chen Chiu , Chih-Kai Kang , Wen-Kai Lin
IPC: H10B20/25
Abstract: A method for fabricating a semiconductor device includes the steps of first providing a substrate having a transistor region and an one time programmable (OTP) capacitor region, forming a first fin-shaped structure on the transistor region and a second fin-shaped structure on the OTP capacitor region, and then performing an oxidation process to form a gate oxide layer on the first fin-shaped structure and the second fin-shaped structure. Preferably, the first fin-shaped structure and the second fin-shaped structure have different shapes under a cross-section perspective.
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公开(公告)号:US20240387523A1
公开(公告)日:2024-11-21
申请号:US18212188
申请日:2023-06-21
Applicant: UNITED MICROELECTRONICS CORP.
Inventor: Hsin-Hsien Chen , Sheng-Yuan Hsueh , Kun-Szu Tseng , Kuo-Hsing Lee , Chih-Kai Kang
IPC: H01L27/088 , H01L21/8234 , H01L29/06 , H01L29/417 , H01L29/423 , H01L29/78
Abstract: A semiconductor device includes a substrate. A high voltage transistor is disposed within a high voltage region of the substrate. The high voltage transistor includes a first gate dielectric layer disposed on the substrate. A first gate electrode is disposed on the first gate dielectric layer. A first source/drain doping region and a second source/drain doping region are respectively disposed in the substrate at two sides of the first gate electrode. A first silicide layer covers and contacts the first source/drain doping region and a second silicide layer covers and contacts the second source/drain doping region. A first conductive plate penetrates the first silicide layer and contacts the first source/drain doping region. A second conductive plate penetrates the second silicide layer and contacts the second source/drain doping region.
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公开(公告)号:US12133377B2
公开(公告)日:2024-10-29
申请号:US17320234
申请日:2021-05-14
Applicant: UNITED MICROELECTRONICS CORP.
Inventor: Kuo-Hsing Lee , Sheng-Yuan Hsueh , Chi-Horn Pai , Chih-Kai Kang
Abstract: A bit cell structure for one-time programming is provided in the present invention, including a substrate, a first doped region in the substrate and electrically connecting a source line, a second doped region in the substrate and having a source and a drain electrically connecting a bit line, a heavily-doped channel in the substrate and connecting the first doped region and the source of second doped region, and a word line crossing over the second dope region between the source and the drain.
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公开(公告)号:US11705512B2
公开(公告)日:2023-07-18
申请号:US17676799
申请日:2022-02-21
Applicant: UNITED MICROELECTRONICS CORP.
Inventor: Kuo-Hsing Lee , Yi-Chung Sheng , Sheng-Yuan Hsueh , Chih-Kai Kang , Guan-Kai Huang , Chien-Liang Wu
IPC: H01L29/778 , H01L29/66
CPC classification number: H01L29/7787 , H01L29/66462
Abstract: A high electron mobility transistor (HEMT) includes a carrier transit layer, a carrier supply layer, a main gate, a control gate, a source electrode and a drain electrode. The carrier transit layer is on a substrate. The carrier supply layer is on the carrier transit layer. The main gate and the control gate are on the carrier supply layer. A fluoride ion doped region is formed right below the main gate in the carrier supply layer. The source electrode and the drain electrode are at two opposite sides of the main gate and the control gate, wherein the source electrode is electrically connected to the control gate by a metal interconnect. The present invention also provides a method of forming a high electron mobility transistor (HEMT).
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公开(公告)号:US20220173236A1
公开(公告)日:2022-06-02
申请号:US17676799
申请日:2022-02-21
Applicant: UNITED MICROELECTRONICS CORP.
Inventor: Kuo-Hsing Lee , Yi-Chung Sheng , Sheng-Yuan Hsueh , Chih-Kai Kang , Guan-Kai Huang , Chien-Liang Wu
IPC: H01L29/778 , H01L29/66
Abstract: A high electron mobility transistor (HEMT) includes a carrier transit layer, a carrier supply layer, a main gate, a control gate, a source electrode and a drain electrode. The carrier transit layer is on a substrate. The carrier supply layer is on the carrier transit layer. The main gate and the control gate are on the carrier supply layer. A fluoride ion doped region is formed right below the main gate in the carrier supply layer. The source electrode and the drain electrode are at two opposite sides of the main gate and the control gate, wherein the source electrode is electrically connected to the control gate by a metal interconnect. The present invention also provides a method of forming a high electron mobility transistor (HEMT).
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公开(公告)号:US20200152768A1
公开(公告)日:2020-05-14
申请号:US16741725
申请日:2020-01-13
Applicant: UNITED MICROELECTRONICS CORP.
Inventor: Kuo-Hsing Lee , Yi-Chung Sheng , Sheng-Yuan Hsueh , Chih-Kai Kang
IPC: H01L29/66 , H01L21/8238 , H01L27/092 , H01L29/78 , H01L27/088 , H01L21/8234
Abstract: A method of forming a fin forced stack inverter includes the following steps. A substrate including a first fin, a second fin and a third fin across a first active area along a first direction is provided, wherein the first fin, the second fin and the third fin are arranged side by side. A fin remove inside active process is performed to remove at least a part of the second fin in the first active area. A first gate is formed across the first fin and the third fin in the first active area along a second direction. The present invention also provides a 1-1 fin forced fin stack inverter formed by said method.
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公开(公告)号:US20190252518A1
公开(公告)日:2019-08-15
申请号:US15912526
申请日:2018-03-05
Applicant: UNITED MICROELECTRONICS CORP.
Inventor: Kuo-Hsing Lee , Yi-Chung Sheng , Sheng-Yuan Hsueh , Chih-Kai Kang
IPC: H01L29/66 , H01L21/8238 , H01L27/092 , H01L29/78
Abstract: A method of forming a fin forced stack inverter includes the following steps. A substrate including a first fin, a second fin and a third fin across a first active area along a first direction is provided, wherein the first fin, the second fin and the third fin are arranged side by side. A fin remove inside active process is performed to remove at least a part of the second fin in the first active area. A first gate is formed across the first fin and the third fin in the first active area along a second direction. The present invention also provides a 1-1 fin forced fin stack inverter formed by said method.
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