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公开(公告)号：US10002864B1
公开(公告)日：2018-06-19
申请号：US15365906
申请日：2016-11-30
发明人： Hsin-Hsien Chen , Sheng-Yuan Hsueh , Yi-Chung Sheng , Chih-Kai Kang , Wen-Kai Lin , Shu-Hung Yu
IPC分类号： H01L29/06 , H01L27/06 , H01L49/02 , H01L23/528 , H01L21/768
摘要： An intra-metal capacitor is provided. The intra-metal capacitor is formed in a dielectric layer and comprising a first electrode and a second electrode, wherein the first electrode penetrate through the whole thickness of the dielectric layer, and the second electrode does not penetrate through the whole thickness of the dielectric layer.
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公开(公告)号：US20240153812A1
公开(公告)日：2024-05-09
申请号：US18074511
申请日：2022-12-04
发明人： Wen-Kai Lin , Chi-Horn Pai , Sheng-Yuan Hsueh , Kuo-Hsing Lee , Chih-Kai Kang
IPC分类号： H01L21/762 , H01L21/768 , H01L29/66
CPC分类号： H01L21/762 , H01L21/76831 , H01L21/76897 , H01L29/66545
摘要： A method for fabricating a semiconductor device includes the steps of first forming a shallow trench isolation (STI) in a substrate, forming a first gate structure on the substrate and adjacent to the STI, forming a first doped region between the first gate structure and the STI, forming a second doped region between the first doped region and the first gate structure, forming a first contact plug on the first doped region, and then forming a second contact plug on the second doped region.
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公开(公告)号：US20180151555A1
公开(公告)日：2018-05-31
申请号：US15365906
申请日：2016-11-30
发明人： Hsin-Hsien Chen , Sheng-Yuan Hsueh , Yi-Chung Sheng , Chih-Kai Kang , Wen-Kai Lin , Shu-Hung Yu
IPC分类号： H01L27/06 , H01L49/02 , H01L29/06 , H01L23/528 , H01L21/768
CPC分类号： H01L27/0629 , H01L21/76897 , H01L23/5283 , H01L28/60 , H01L29/0649
摘要： An intra-metal capacitor is provided. The intra-metal capacitor is formed in a dielectric layer and comprising a first electrode and a second electrode, wherein the first electrode penetrate through the whole thickness of the dielectric layer, and the second electrode does not penetrate through the whole thickness of the dielectric layer.
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公开(公告)号：US11854632B2
公开(公告)日：2023-12-26
申请号：US17502056
申请日：2021-10-15
发明人： Kuo-Hsing Lee , Chien-Liang Wu , Wen-Kai Lin , Te-Wei Yeh , Sheng-Yuan Hsueh , Chi-Horn Pai
CPC分类号： G11C17/165 , G11C16/10 , H10B20/20 , H10B20/25 , G11C2216/26
摘要： A semiconductor memory structure includes a substrate having thereon a transistor forming region and a capacitor forming region. A transistor is disposed on the substrate within the transistor forming region. A capacitor is disposed within the capacitor forming region and electrically coupled to the transistor. A first inter-layer dielectric layer covers the transistor forming region and the capacitor forming region. The first inter-layer dielectric layer surrounds a metal gate of the transistor and a bottom plate of the capacitor. A cap layer is disposed on the first inter-layer dielectric layer. The cap layer has a first thickness within the transistor forming region and a second thickness within the capacitor forming region. The first thickness is greater than the second thickness. The cap layer within the capacitor forming region acts as a capacitor dielectric layer of the capacitor.
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公开(公告)号：US10529707B2
公开(公告)日：2020-01-07
申请号：US15983096
申请日：2018-05-18
发明人： Hsin-Hsien Chen , Sheng-Yuan Hsueh , Yi-Chung Sheng , Chih-Kai Kang , Wen-Kai Lin , Shu-Hung Yu
IPC分类号： H01L27/06 , H01L21/768 , H01L29/06 , H01L49/02 , H01L23/528
摘要： A method of forming a capacitor includes the following steps. First, a substrate is provided. A dielectric layer is formed over the substrate. A first patterning process is performed to form a first contact plug through the whole thickness of the dielectric layer and a second patterning process is performed to form a second contact plug in the dielectric layer and spaced apart from the first contact plug in a pre-determined distance, wherein the first contact plug and the second contact plug are capacitively coupled.
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公开(公告)号：US10256155B1
公开(公告)日：2019-04-09
申请号：US15893709
申请日：2018-02-12
发明人： Wen-Kai Lin , Yi-Chung Sheng , Sheng-Yuan Hsueh , Chih-Kai Kang
IPC分类号： H01L29/78 , H01L21/762 , H01L23/528 , H01L27/088 , H01L21/8234
摘要： A method for fabricating semiconductor device includes the steps of: forming a first active region and a second active region extending along a first direction on a substrate; forming a first single diffusion break (SDB) structure extending along a second direction between the first active region and the second active region; and forming a first gate line extending along the second direction intersecting the first active region and the second active region. Preferably, the first SDB structure is directly under the first gate line between the first active region and the second active region.
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公开(公告)号：US20180156862A1
公开(公告)日：2018-06-07
申请号：US15369905
申请日：2016-12-06
IPC分类号： G01R31/28
CPC分类号： G01R31/2884 , H01L22/14 , H01L22/34
摘要： The present invention provides a test key structure for measuring or simulating a target via array. The structure includes a substrate with a test region, a plurality of first conductive lines in the test region; a plurality of second conductive lines in the test region and on the first conductive lines, wherein the first conductive lines and the second conductive lines overlaps vertically in a plurality of target regions, and a plurality of vias disposed between the first conductive lines and the second conductive lines, wherein at least two vias vertically contact one of the first conductive lines and one of the second conductive lines. The present invention further provides a method of measuring resistance by using the testkey structure
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公开(公告)号：US20230081533A1
公开(公告)日：2023-03-16
申请号：US17502056
申请日：2021-10-15
发明人： Kuo-Hsing Lee , Chien-Liang Wu , Wen-Kai Lin , Te-Wei Yeh , Sheng-Yuan Hsueh , Chi-Horn Pai
摘要： A semiconductor memory structure includes a substrate having thereon a transistor forming region and a capacitor forming region. A transistor is disposed on the substrate within the transistor forming region. A capacitor is disposed within the capacitor forming region and electrically coupled to the transistor. A first inter-layer dielectric layer covers the transistor forming region and the capacitor forming region. The first inter-layer dielectric layer surrounds a metal gate of the transistor and a bottom plate of the capacitor. A cap layer is disposed on the first inter-layer dielectric layer. The cap layer has a first thickness within the transistor forming region and a second thickness within the capacitor forming region. The first thickness is greater than the second thickness. The cap layer within the capacitor forming region acts as a capacitor dielectric layer of the capacitor.
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公开(公告)号：US10247774B2
公开(公告)日：2019-04-02
申请号：US15369905
申请日：2016-12-06
摘要： The present invention provides a test key structure for measuring or simulating a target via array. The structure includes a substrate with a test region, a plurality of first conductive lines in the test region; a plurality of second conductive lines in the test region and on the first conductive lines, wherein the first conductive lines and the second conductive lines overlaps vertically in a plurality of target regions, and a plurality of vias disposed between the first conductive lines and the second conductive lines, wherein at least two vias vertically contact one of the first conductive lines and one of the second conductive lines. The present invention further provides a method of measuring resistance by using the testkey structure.
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公开(公告)号：US20180269201A1
公开(公告)日：2018-09-20
申请号：US15983096
申请日：2018-05-18
发明人： Hsin-Hsien Chen , Sheng-Yuan Hsueh , Yi-Chung Sheng , Chih-Kai Kang , Wen-Kai Lin , Shu-Hung Yu
IPC分类号： H01L27/06 , H01L29/06 , H01L23/528 , H01L49/02 , H01L21/768
CPC分类号： H01L27/0629 , H01L21/76897 , H01L23/485 , H01L23/5223 , H01L23/5283 , H01L28/60 , H01L29/0649
摘要： A method of forming a capacitor includes the following steps. First, a substrate is provided. A dielectric layer is formed over the substrate. A first patterning process is performed to form a first contact plug through the whole thickness of the dielectric layer and a second patterning process is performed to form a second contact plug in the dielectric layer and spaced apart from the first contact plug in a pre-determined distance, wherein the first contact plug and the second contact plug are capacitively coupled.
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