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    STATIC RANDOM ACCESS MEMORY
    1.
    发明申请
    STATIC RANDOM ACCESS MEMORY 有权

    公开(公告)号：US20240397689A1

    公开(公告)日：2024-11-28

    申请号：US18337434

    申请日：2023-06-20

    Applicant: United Microelectronics Corp.

    Inventor： Hsin-Hsien Chen ,  Sheng-Yuan Hsueh ,  Chih-Kai Kang ,  Kuo-Hsing Lee

    IPC: H10B10/00

    Abstract: A static random access memory (SRAM) includes a first memory cell. The first memory cell includes: a first pull-down transistor, a first pull-up transistor, a second pull-up transistor, and a second pull-down transistor arranged on a first segment of a first fin, a first segment of a second fin, a first segment of a third fin and a first segment of a fourth fin of a substrate, respectively. The first memory cell further includes a first diode and a second diode. The first diode includes a first conductive feature in contact with a top surface and multiple upper sidewalls of a first end of the first segment of the first fin. The second diode includes a second conductive feature in contact with a top surface and multiple upper sidewalls of a second end of the first segment of the fourth fin.

    TEST KEY STRUCTURE AND METHOD OF MEASURING RESISTANCE OF VIAS
    5.
    发明申请
    TEST KEY STRUCTURE AND METHOD OF MEASURING RESISTANCE OF VIAS 审中-公开

    公开(公告)号：US20180156862A1

    公开(公告)日：2018-06-07

    申请号：US15369905

    申请日：2016-12-06

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Hsin-Hsien Chen ,  Sheng-Yuan Hsueh ,  Yi-Chung Sheng ,  Wen-Kai Lin ,  Chih-Kai Kang

    IPC: G01R31/28

    CPC classification number: G01R31/2884 ,  H01L22/14 ,  H01L22/34

    Abstract: The present invention provides a test key structure for measuring or simulating a target via array. The structure includes a substrate with a test region, a plurality of first conductive lines in the test region; a plurality of second conductive lines in the test region and on the first conductive lines, wherein the first conductive lines and the second conductive lines overlaps vertically in a plurality of target regions, and a plurality of vias disposed between the first conductive lines and the second conductive lines, wherein at least two vias vertically contact one of the first conductive lines and one of the second conductive lines. The present invention further provides a method of measuring resistance by using the testkey structure

    SEMICONDUCTOR DEVICE AND FABRICATING METHOD OF THE SAME
    6.
    发明申请
    SEMICONDUCTOR DEVICE AND FABRICATING METHOD OF THE SAME 有权

    公开(公告)号：US20240387523A1

    公开(公告)日：2024-11-21

    申请号：US18212188

    申请日：2023-06-21

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Hsin-Hsien Chen ,  Sheng-Yuan Hsueh ,  Kun-Szu Tseng ,  Kuo-Hsing Lee ,  Chih-Kai Kang

    IPC: H01L27/088 ,  H01L21/8234 ,  H01L29/06 ,  H01L29/417 ,  H01L29/423 ,  H01L29/78

    Abstract: A semiconductor device includes a substrate. A high voltage transistor is disposed within a high voltage region of the substrate. The high voltage transistor includes a first gate dielectric layer disposed on the substrate. A first gate electrode is disposed on the first gate dielectric layer. A first source/drain doping region and a second source/drain doping region are respectively disposed in the substrate at two sides of the first gate electrode. A first silicide layer covers and contacts the first source/drain doping region and a second silicide layer covers and contacts the second source/drain doping region. A first conductive plate penetrates the first silicide layer and contacts the first source/drain doping region. A second conductive plate penetrates the second silicide layer and contacts the second source/drain doping region.

    Test key structure and method of measuring resistance of vias
    7.
    发明授权
    Test key structure and method of measuring resistance of vias 有权

    公开(公告)号：US10247774B2

    公开(公告)日：2019-04-02

    申请号：US15369905

    申请日：2016-12-06

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Hsin-Hsien Chen ,  Sheng-Yuan Hsueh ,  Yi-Chung Sheng ,  Wen-Kai Lin ,  Chih-Kai Kang

    IPC: G01R31/28 ,  H01L21/66

    Abstract: The present invention provides a test key structure for measuring or simulating a target via array. The structure includes a substrate with a test region, a plurality of first conductive lines in the test region; a plurality of second conductive lines in the test region and on the first conductive lines, wherein the first conductive lines and the second conductive lines overlaps vertically in a plurality of target regions, and a plurality of vias disposed between the first conductive lines and the second conductive lines, wherein at least two vias vertically contact one of the first conductive lines and one of the second conductive lines. The present invention further provides a method of measuring resistance by using the testkey structure.

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