公开(公告)号：US12133377B2

公开(公告)日：2024-10-29

申请号：US17320234

申请日：2021-05-14

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Kuo-Hsing Lee ,  Sheng-Yuan Hsueh ,  Chi-Horn Pai ,  Chih-Kai Kang

IPC: H10B20/20 ,  G11C17/16

CPC classification number: H10B20/20 ,  G11C17/16

Abstract: A bit cell structure for one-time programming is provided in the present invention, including a substrate, a first doped region in the substrate and electrically connecting a source line, a second doped region in the substrate and having a source and a drain electrically connecting a bit line, a heavily-doped channel in the substrate and connecting the first doped region and the source of second doped region, and a word line crossing over the second dope region between the source and the drain.

公开(公告)号：US20230247827A1

公开(公告)日：2023-08-03

申请号：US18134041

申请日：2023-04-13

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Kuo-Hsing Lee ,  Chang-Chien Wong ,  Sheng-Yuan Hsueh ,  Ching-Hsiang Tseng ,  Chi-Horn Pai ,  Shih-Chieh Hsu

IPC: H10B20/25

CPC classification number: H10B20/25

Abstract: A one-time programmable (OTP) memory cell includes a substrate having an active area surrounded by an isolation region. A divot is disposed between the active area and the isolation region. A transistor is disposed on the active area. A diffusion-contact fuse is electrically coupled to the transistor. The diffusion-contact fuse includes a diffusion region in the active area, a silicide layer on the diffusion region, and a contact partially landed on the silicide layer and partially landed on the isolation region. A sidewall surface of the diffusion region in the divot is covered by the silicide layer. The divot is filled with the contact.

公开(公告)号：US11665891B2

公开(公告)日：2023-05-30

申请号：US17314061

申请日：2021-05-07

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Kuo-Hsing Lee ,  Chang-Chien Wong ,  Sheng-Yuan Hsueh ,  Ching-Hsiang Tseng ,  Chi-Horn Pai ,  Shih-Chieh Hsu

IPC: H10B20/20

CPC classification number: H10B20/20

Abstract: A one-time programmable (OTP) memory cell includes a substrate comprising an active area surrounded by an isolation region, a transistor disposed on the active area, and a diffusion-contact fuse electrically coupled to the transistor. The diffusion-contact fuse includes a diffusion region in the active area, a silicide layer on the diffusion region, and a contact partially landed on the silicide layer and partially landed on the isolation region.

公开(公告)号：US20230081533A1

公开(公告)日：2023-03-16

申请号：US17502056

申请日：2021-10-15

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Kuo-Hsing Lee ,  Chien-Liang Wu ,  Wen-Kai Lin ,  Te-Wei Yeh ,  Sheng-Yuan Hsueh ,  Chi-Horn Pai

IPC: G11C17/16 ,  G11C16/10

Abstract: A semiconductor memory structure includes a substrate having thereon a transistor forming region and a capacitor forming region. A transistor is disposed on the substrate within the transistor forming region. A capacitor is disposed within the capacitor forming region and electrically coupled to the transistor. A first inter-layer dielectric layer covers the transistor forming region and the capacitor forming region. The first inter-layer dielectric layer surrounds a metal gate of the transistor and a bottom plate of the capacitor. A cap layer is disposed on the first inter-layer dielectric layer. The cap layer has a first thickness within the transistor forming region and a second thickness within the capacitor forming region. The first thickness is greater than the second thickness. The cap layer within the capacitor forming region acts as a capacitor dielectric layer of the capacitor.

公开(公告)号：US20250014661A1

公开(公告)日：2025-01-09

申请号：US18890725

申请日：2024-09-19

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Kuo-Hsing Lee ,  Sheng-Yuan Hsueh ,  Chi-Horn Pai ,  Chih-Kai Kang

IPC: G11C17/16 ,  H10B20/25

Abstract: A bit cell structure for one-time-programming is provided in the present invention, including a first doped region in a substrate and electrically connected to a source line, a second doped region in the substrate and provided with a source and a drain, wherein the drain is electrically connected with a bit line, a doped channel region in the substrate with a first part and a second part connecting respectively to the first doped region and the source of second doped region in a first direction, and a width of the first part in a second direction perpendicular to the first direction is less than a width of the second part and less than a width of the first doped region, and a word line traversing over the second doped region and between the source and drain.

公开(公告)号：US20240153812A1

公开(公告)日：2024-05-09

申请号：US18074511

申请日：2022-12-04

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Wen-Kai Lin ,  Chi-Horn Pai ,  Sheng-Yuan Hsueh ,  Kuo-Hsing Lee ,  Chih-Kai Kang

IPC: H01L21/762 ,  H01L21/768 ,  H01L29/66

CPC classification number: H01L21/762 ,  H01L21/76831 ,  H01L21/76897 ,  H01L29/66545

Abstract: A method for fabricating a semiconductor device includes the steps of first forming a shallow trench isolation (STI) in a substrate, forming a first gate structure on the substrate and adjacent to the STI, forming a first doped region between the first gate structure and the STI, forming a second doped region between the first doped region and the first gate structure, forming a first contact plug on the first doped region, and then forming a second contact plug on the second doped region.

公开(公告)号：US20220328504A1

公开(公告)日：2022-10-13

申请号：US17320234

申请日：2021-05-14

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Kuo-Hsing Lee ,  Sheng-Yuan Hsueh ,  Chi-Horn Pai ,  Chih-Kai Kang

IPC: H01L27/112 ,  G11C17/16

Abstract: A bit cell structure for one-time programming is provided in the present invention, including a substrate, a first doped region in the substrate and electrically connecting a source line, a second doped region in the substrate and having a source and a drain electrically connecting a bit line, a heavily-doped channel in the substrate and connecting the first doped region and the source of second doped region, and a word line crossing over the second dope region between the source and the drain.

公开(公告)号：US20220328503A1

公开(公告)日：2022-10-13

申请号：US17314061

申请日：2021-05-07

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Kuo-Hsing Lee ,  Chang-Chien Wong ,  Sheng-Yuan Hsueh ,  Ching-Hsiang Tseng ,  Chi-Horn Pai ,  Shih-Chieh Hsu

IPC: H01L27/112

Abstract: A one-time programmable (OTP) memory cell includes a substrate comprising an active area surrounded by an isolation region, a transistor disposed on the active area, and a diffusion-contact fuse electrically coupled to the transistor. The diffusion-contact fuse includes a diffusion region in the active area, a silicide layer on the diffusion region, and a contact partially landed on the silicide layer and partially landed on the isolation region.

公开(公告)号：US11854632B2

公开(公告)日：2023-12-26

申请号：US17502056

申请日：2021-10-15

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Kuo-Hsing Lee ,  Chien-Liang Wu ,  Wen-Kai Lin ,  Te-Wei Yeh ,  Sheng-Yuan Hsueh ,  Chi-Horn Pai

IPC: G11C17/16 ,  G11C16/10 ,  H10B20/25 ,  H10B20/20

CPC classification number: G11C17/165 ,  G11C16/10 ,  H10B20/20 ,  H10B20/25 ,  G11C2216/26

Abstract: A semiconductor memory structure includes a substrate having thereon a transistor forming region and a capacitor forming region. A transistor is disposed on the substrate within the transistor forming region. A capacitor is disposed within the capacitor forming region and electrically coupled to the transistor. A first inter-layer dielectric layer covers the transistor forming region and the capacitor forming region. The first inter-layer dielectric layer surrounds a metal gate of the transistor and a bottom plate of the capacitor. A cap layer is disposed on the first inter-layer dielectric layer. The cap layer has a first thickness within the transistor forming region and a second thickness within the capacitor forming region. The first thickness is greater than the second thickness. The cap layer within the capacitor forming region acts as a capacitor dielectric layer of the capacitor.

公开(公告)号：US20230378167A1

公开(公告)日：2023-11-23

申请号：US17844742

申请日：2022-06-21

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Kuo-Hsing Lee ,  Chun-Hsien Lin ,  Yung-Chen Chiu ,  Sheng-Yuan Hsueh ,  Chi-Horn Pai

IPC: H01L27/06 ,  H01L21/8234

CPC classification number: H01L27/0629 ,  H01L21/823456 ,  H01L21/823475 ,  H01L21/823481 ,  H01L21/823431

Abstract: The present disclosure provides, the semiconductor device includes a substrate, a first transistor, a capacitor, and two first plugs. The substrate has a high-voltage region and a capacitor region. The first transistor is disposed in the high-voltage region, and includes a first gate dielectric layer, a first gate electrode, and a first capping layer. The capacitor is disposed in the capacitor region and includes a second gate electrode, a second capping layer, a dielectric layer, and a conductive layer. The two first plugs are disposed on the capacitor, wherein one of the two first plugs penetrates through the second capping layer to directly contact the second gate electrode, and another one of the two first plugs directly contacts the conductive layer.