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18 条记录 (耗时 0.017 秒)

    BIT CELL STRUCTURE FOR ONE-TIME-PROGRAMMING
    2.
    发明申请
    BIT CELL STRUCTURE FOR ONE-TIME-PROGRAMMING 有权

    公开(公告)号：US20220328504A1

    公开(公告)日：2022-10-13

    申请号：US17320234

    申请日：2021-05-14

    申请人： UNITED MICROELECTRONICS CORP.

    发明人： Kuo-Hsing Lee ,  Sheng-Yuan Hsueh ,  Chi-Horn Pai ,  Chih-Kai Kang

    IPC分类号： H01L27/112 ,  G11C17/16

    摘要： A bit cell structure for one-time programming is provided in the present invention, including a substrate, a first doped region in the substrate and electrically connecting a source line, a second doped region in the substrate and having a source and a drain electrically connecting a bit line, a heavily-doped channel in the substrate and connecting the first doped region and the source of second doped region, and a word line crossing over the second dope region between the source and the drain.

    ONE-TIME PROGRAMMABLE MEMORY CELL
    5.
    发明公开
    ONE-TIME PROGRAMMABLE MEMORY CELL 审中-公开

    公开(公告)号：US20230247827A1

    公开(公告)日：2023-08-03

    申请号：US18134041

    申请日：2023-04-13

    申请人： UNITED MICROELECTRONICS CORP.

    发明人： Kuo-Hsing Lee ,  Chang-Chien Wong ,  Sheng-Yuan Hsueh ,  Ching-Hsiang Tseng ,  Chi-Horn Pai ,  Shih-Chieh Hsu

    IPC分类号： H10B20/25

    CPC分类号： H10B20/25

    摘要： A one-time programmable (OTP) memory cell includes a substrate having an active area surrounded by an isolation region. A divot is disposed between the active area and the isolation region. A transistor is disposed on the active area. A diffusion-contact fuse is electrically coupled to the transistor. The diffusion-contact fuse includes a diffusion region in the active area, a silicide layer on the diffusion region, and a contact partially landed on the silicide layer and partially landed on the isolation region. A sidewall surface of the diffusion region in the divot is covered by the silicide layer. The divot is filled with the contact.

    SEMICONDUCTOR MEMORY STRUCTURE AND FABRICATION METHOD THEREOF
    7.
    发明申请
    SEMICONDUCTOR MEMORY STRUCTURE AND FABRICATION METHOD THEREOF 有权

    公开(公告)号：US20230081533A1

    公开(公告)日：2023-03-16

    申请号：US17502056

    申请日：2021-10-15

    申请人： UNITED MICROELECTRONICS CORP.

    发明人： Kuo-Hsing Lee ,  Chien-Liang Wu ,  Wen-Kai Lin ,  Te-Wei Yeh ,  Sheng-Yuan Hsueh ,  Chi-Horn Pai

    IPC分类号： G11C17/16 ,  G11C16/10

    摘要： A semiconductor memory structure includes a substrate having thereon a transistor forming region and a capacitor forming region. A transistor is disposed on the substrate within the transistor forming region. A capacitor is disposed within the capacitor forming region and electrically coupled to the transistor. A first inter-layer dielectric layer covers the transistor forming region and the capacitor forming region. The first inter-layer dielectric layer surrounds a metal gate of the transistor and a bottom plate of the capacitor. A cap layer is disposed on the first inter-layer dielectric layer. The cap layer has a first thickness within the transistor forming region and a second thickness within the capacitor forming region. The first thickness is greater than the second thickness. The cap layer within the capacitor forming region acts as a capacitor dielectric layer of the capacitor.

    ONE-TIME PROGRAMMABLE MEMORY STRUCTURE
    9.
    发明申请
    ONE-TIME PROGRAMMABLE MEMORY STRUCTURE 有权

    公开(公告)号：US20220336479A1

    公开(公告)日：2022-10-20

    申请号：US17323863

    申请日：2021-05-18

    申请人： United Microelectronics Corp.

    发明人： Kuo-Hsing Lee ,  Chi-Horn Pai ,  Chang Chien Wong ,  Sheng-Yuan Hsueh ,  Ching Hsiang Tseng ,  Shih-Chieh Hsu

    IPC分类号： H01L27/112

    摘要： A one-time programmable memory structure including a substrate, a transistor, a capacitor, and an interconnect structure is provided. The transistor is located on the substrate. The capacitor includes a first electrode, a second electrode, and an insulating layer. The first electrode is disposed above the substrate. The second electrode is disposed on the first electrode. The first electrode is located between the second electrode and the substrate. The insulating layer is disposed between the first electrode and the second electrode. The interconnect structure is electrically connected between the transistor and the first electrode of the capacitor. The interconnect structure is electrically connected to the first electrode at a top surface of the first electrode.