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公开(公告)号：US20230378166A1
公开(公告)日：2023-11-23
申请号：US17844088
申请日：2022-06-20
CPC分类号： H01L27/0629 , H01L28/20 , H01L29/7851 , H01L29/66795
摘要： A method for fabricating a semiconductor device includes the steps of first providing a substrate having a resistor region, forming a first gate structure on the resistor region, forming a first interlayer dielectric (ILD) layer around the first gate structure, transforming the first gate structure into a first metal gate having a gate electrode on the substrate and a hard mask on the gate electrode, and then forming a resistor on the first metal gate.
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公开(公告)号：US20230422491A1
公开(公告)日：2023-12-28
申请号：US17869752
申请日：2022-07-20
发明人： Yung-Chen Chiu , Chi-Horn Pai , Sheng-Yuan Hsueh , Kuo-Hsing Lee , Chih-Kai Kang
IPC分类号： H01L27/112
CPC分类号： H01L27/11206
摘要： A method for fabricating a semiconductor device includes the steps of first providing a substrate comprising an one time programmable (OTP) device region, forming a shallow trench isolation (STI) in the substrate, removing part of the STI to form a first step on a corner of the substrate, forming a first gate oxide layer on the substrate, removing the first gate oxide layer to form a second step on the corner of the substrate, forming a second gate oxide layer on the substrate, and then forming a first gate structure on the substrate and the STI.
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公开(公告)号：US11765891B2
公开(公告)日：2023-09-19
申请号：US17391067
申请日：2021-08-02
发明人： Kuo-Hsing Lee , Sheng-Yuan Hsueh , Chun-Hsien Lin , Yung-Chen Chiu , Chien-Liang Wu , Te-Wei Yeh
摘要： A one-time programmable (OTP) memory cell includes a substrate having a first conductivity type and having an active area surrounded by an isolation region, a transistor disposed on the active area, and a capacitor disposed on the active area and electrically coupled to the transistor. The capacitor comprises a diffusion region of a second conductivity type in the substrate, a metallic film in direct contact with the active area, a capacitor dielectric layer on the metallic film, and a metal gate surrounded by the capacitor dielectric layer. The diffusion region and the metallic film constitute a capacitor bottom plate.
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公开(公告)号：US20230378167A1
公开(公告)日：2023-11-23
申请号：US17844742
申请日：2022-06-21
IPC分类号： H01L27/06 , H01L21/8234
CPC分类号： H01L27/0629 , H01L21/823456 , H01L21/823475 , H01L21/823481 , H01L21/823431
摘要： The present disclosure provides, the semiconductor device includes a substrate, a first transistor, a capacitor, and two first plugs. The substrate has a high-voltage region and a capacitor region. The first transistor is disposed in the high-voltage region, and includes a first gate dielectric layer, a first gate electrode, and a first capping layer. The capacitor is disposed in the capacitor region and includes a second gate electrode, a second capping layer, a dielectric layer, and a conductive layer. The two first plugs are disposed on the capacitor, wherein one of the two first plugs penetrates through the second capping layer to directly contact the second gate electrode, and another one of the two first plugs directly contacts the conductive layer.
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公开(公告)号：US20230015480A1
公开(公告)日：2023-01-19
申请号：US17391067
申请日：2021-08-02
发明人： Kuo-Hsing Lee , Sheng-Yuan Hsueh , Chun-Hsien Lin , Yung-Chen Chiu , Chien-Liang Wu , Te-Wei Yeh
IPC分类号： H01L27/112
摘要： A one-time programmable (OTP) memory cell includes a substrate having a first conductivity type and having an active area surrounded by an isolation region, a transistor disposed on the active area, and a capacitor disposed on the active area and electrically coupled to the transistor. The capacitor comprises a diffusion region of a second conductivity type in the substrate, a metallic film in direct contact with the active area, a capacitor dielectric layer on the metallic film, and a metal gate surrounded by the capacitor dielectric layer. The diffusion region and the metallic film constitute a capacitor bottom plate.
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公开(公告)号：US20220059528A1
公开(公告)日：2022-02-24
申请号：US17516721
申请日：2021-11-02
发明人： Yung-Chen Chiu , Sheng-Yuan Hsueh , Kuo-Hsing Lee , Chien-Liang Wu , Chih-Kai Kang , Guan-Kai Huang
IPC分类号： H01L27/06 , H01L27/085 , H01L29/66 , H01L29/778
摘要： A 3D semiconductor structure includes a buffer layer, a n-type high electron mobility transistor (HEMT) disposed on a first surface of the buffer layer, and a p-type high hole mobility transistor (HHMT) disposed on a second surface of the buffer layer opposite to the first surface.
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公开(公告)号：US11605631B2
公开(公告)日：2023-03-14
申请号：US17516721
申请日：2021-11-02
发明人： Yung-Chen Chiu , Sheng-Yuan Hsueh , Kuo-Hsing Lee , Chien-Liang Wu , Chih-Kai Kang , Guan-Kai Huang
IPC分类号： H01L27/085 , H01L27/06 , H01L29/66 , H01L29/778
摘要： A 3D semiconductor structure includes a buffer layer, a n-type high electron mobility transistor (HEMT) disposed on a first surface of the buffer layer, and a p-type high hole mobility transistor (HHMT) disposed on a second surface of the buffer layer opposite to the first surface.
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公开(公告)号：US11195831B2
公开(公告)日：2021-12-07
申请号：US16596764
申请日：2019-10-09
发明人： Yung-Chen Chiu , Sheng-Yuan Hsueh , Kuo-Hsing Lee , Chien-Liang Wu , Chih-Kai Kang , Guan-Kai Huang
IPC分类号： H01L29/778 , H01L27/06 , H01L27/085 , H01L29/66
摘要： A 3D semiconductor structure includes a buffer layer, a n-type high electron mobility transistor (HEMT) disposed on a first surface of the buffer layer, and a p-type high hole mobility transistor (HHMT) disposed on a second surface of the buffer layer opposite to the first surface.
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公开(公告)号：US20210082911A1
公开(公告)日：2021-03-18
申请号：US16596764
申请日：2019-10-09
发明人： Yung-Chen Chiu , Sheng-Yuan Hsueh , Kuo-Hsing Lee , Chien-Liang Wu , Chih-Kai Kang , Guan-Kai Huang
IPC分类号： H01L27/06 , H01L29/778 , H01L29/66 , H01L27/085
摘要： A 3D semiconductor structure includes a buffer layer, a n-type high electron mobility transistor (HEMT) disposed on a first surface of the buffer layer, and a p-type high hole mobility transistor (HHMT) disposed on a second surface of the buffer layer opposite to the first surface.
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