公开(公告)号：US20240047554A1

公开(公告)日：2024-02-08

申请号：US17899604

申请日：2022-08-30

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Zhi-Cheng Lee ,  Huai-Tzu Chiang ,  Chuang-Han Hsieh ,  Kai-Lin Lee

IPC: H01L29/66 ,  H01L29/778 ,  H01L23/31

CPC classification number: H01L29/66462 ,  H01L29/778 ,  H01L23/3171 ,  H01L23/3192 ,  H01L29/2003

Abstract: A manufacturing method of a semiconductor device includes the following steps. A III-V compound barrier layer is formed on a III-V compound semiconductor layer. A protection layer is formed on the III-V compound barrier layer. An opening is formed penetrating through the protection layer in a vertical direction and exposing a part of the III-V compound barrier layer. A p-type doped III-V compound material is formed in the opening. A patterned barrier layer is formed on the p-type doped III-V compound material. A contact area between the patterned barrier layer and the p-type doped III-V compound material is less than an area of a top surface of the p-type doped III-V compound material.

公开(公告)号：US20240021702A1

公开(公告)日：2024-01-18

申请号：US17885574

申请日：2022-08-11

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Zhi-Cheng Lee ,  Chuang-Han Hsieh ,  Huai-Tzu Chiang ,  Kai-Lin Lee

IPC: H01L29/66 ,  H01L29/20 ,  H01L29/778

CPC classification number: H01L29/66462 ,  H01L29/2003 ,  H01L29/7786

Abstract: An HEMT includes a first III-V compound layer, a second III-V compound layer, and a III-V compound cap layer. The second III-V compound layer is disposed on the first III-V compound layer. The III-V compound cap layer covers and contacts the second III-V compound layer. The composition of the III-V compound cap layer and the second III-V compound layer are different from each other. A first opening is disposed in the III-V compound cap layer. A first insulating layer includes two first insulating parts and two second insulating parts. The two first insulating parts cover a top surface of the III-V compound cap layer, and the two second insulating parts respectively contact two sidewalls of the first opening. A second opening is disposed between the two first insulating parts and between the two second insulating parts. A gate electrode is disposed in the second opening.

公开(公告)号：US20180358453A1

公开(公告)日：2018-12-13

申请号：US15642360

申请日：2017-07-06

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Hung-Wen Huang ,  Kai-Lin Lee ,  Ren-Yu He ,  Chi-Hsiao Chen ,  Ting-Hsuan Kang ,  Hao-Hsiang Yang ,  An-Shih Shih ,  Chuang-Han Hsieh

IPC: H01L29/66 ,  H01L29/49 ,  H01L29/786 ,  H01L21/28

CPC classification number: H01L29/66977 ,  H01L21/28088 ,  H01L29/4908 ,  H01L29/66742 ,  H01L29/78696

Abstract: The present invention provides a method of making a tunneling effect transistor (TFET), the method includes: a substrate is provided, having a fin structure disposed thereon, the fin structure includes a first conductive type, a dielectric layer is then formed on the substrate and on the fin structure, a gate trench is formed in the dielectric layer, and a first work function metal layer is formed in the gate trench, the first work function metal layer defines at least a left portion, a right portion and a central portion, an etching process is performed to remove the central portion of the first work function metal layer, and to form a recess between the left portion and the right portion of the first work function metal layer, afterwards, a second work function metal layer is formed and filled in the recess.