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公开(公告)号：US20200227420A1
公开(公告)日：2020-07-16
申请号：US16828966
申请日：2020-03-25
Inventor： Wen-Fu Huang , Fu-Che Lee
IPC: H01L27/108 , H01L21/02 , H01L21/311
Abstract: A method for fabricating semiconductor device includes the steps of: providing a substrate having a memory region and a logic region; forming a stack structure on the memory region and a gate structure on the logic region; forming a first cap layer on the stack structure and the gate structure; performing an oxidation process to form an oxide layer on the first cap layer; forming a second cap layer on the oxide layer; and removing part of the second cap layer, part of the oxide layer, and part of the first cap layer on the logic region to form a spacer adjacent to the gate structure.
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公开(公告)号：US10672648B2
公开(公告)日：2020-06-02
申请号：US15937849
申请日：2018-03-27
Inventor： Feng-Yi Chang , Fu-Che Lee , Yi-Wang Zhan
IPC: H01L21/768 , H01L27/108 , H01L21/311
Abstract: A method of forming a semiconductor memory device includes following steps. First of all, a dielectric layer is formed on a semiconductor substrate, and a conductive pad is formed in the dielectric layer. Then, a stacked structure is formed on the dielectric layer, and the stacked structure includes a first layer, a second layer and a third layer stacked one over another on the conductive pad. Next, a patterned mask layer is formed on the stacked structure, and a portion of the stacked structure is removed, to form an opening in the stacked structure, with the opening having a tapered sidewall in the second layer and the first layer. After that, the tapered sidewall of the opening in the second layer is vertically etched, to form a contact opening in the stacked structure. Finally, the patterned mask layer is removed.
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公开(公告)号：US10672612B2
公开(公告)日：2020-06-02
申请号：US15969788
申请日：2018-05-03
Inventor： Gang-Yi Lin , Feng-Yi Chang , Ying-Chih Lin , Fu-Che Lee
IPC: H01L21/033 , H01L21/311
Abstract: The present invention provides a method of forming a semiconductor structure including the following steps. Firstly, a target layer is formed on a substrate, and a plurality of mandrels is formed on the target layer. Next, a material layer is formed on the target layer to cover the mandrels. Then, an etching process is performed to partially remove each of the mandrel and the material layer covered on each mandrel, to form a plurality of mask. Finally, the target layer is patterned through the masks, to form a plurality of patterns. Through the present invention, each mask comprises an unetched portion of each mandrel and a spacer portion of the material covered on each mandrel, and a dimension of each of the patterns is larger than a dimension of each of the mandrel.
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公开(公告)号：US10529571B1
公开(公告)日：2020-01-07
申请号：US16262913
申请日：2019-01-31
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Feng-Yi Chang , Fu-Che Lee
IPC: H01L21/308 , H01L21/033 , H01L21/3213
Abstract: A method of fabricating a patterned structure includes the following steps. A pattern transfer layer is formed on a material layer. The pattern transfer layer is formed above a first region and a second region. First patterns are formed on the pattern transfer layer. A mask layer is formed. A first part of the mask layer covers the first patterns above the first region. A first cap layer is formed covering the first part of the mask layer and the first patterns above the second region. The first cap layer covering the first part of the mask layer is removed for exposing the first part of the mask layer. The first part of the mask layer is removed. A first etching process is performed to the pattern transfer layer with the first patterns above the first region as a mask after removing the first part of the mask layer.
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公开(公告)号：US20190341487A1
公开(公告)日：2019-11-07
申请号：US16509475
申请日：2019-07-11
Inventor： Feng-Yi Chang , Yu-Cheng Tung , Fu-Che Lee
IPC: H01L29/78 , H01L27/108 , H01L21/02 , H01L21/762 , H01L21/4757
Abstract: A method of forming a semiconductor structure is disclosed, comprising providing a substrate, forming at least a gate trench extending along a first direction in the substrate, forming a gate dielectric layer conformally covering the gate trench, forming a sacrificial layer on the gate dielectric layer and completely filling the gate trench, forming a plurality of openings through the sacrificial layer in the gate trench thereby exposing a portion of the gate dielectric layer, forming a dielectric material in the openings, performing an etching back process to remove a portion of the dielectric material until the dielectric material only remains at a lower portion of each of the openings thereby obtaining a plurality of intervening structures, removing the sacrificial layer, and forming a gate metal filling the gate trench, wherein the intervening structures are disposed between the gate metal and the gate dielectric layer.
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Patent Agency Ranking
公开(公告)号：US20190333884A1
公开(公告)日：2019-10-31
申请号：US16505724
申请日：2019-07-09
Inventor： Feng-Yi Chang , Fu-Che Lee , Chin-Hsin Chiu
IPC: H01L23/00 , H01L21/768 , H01L23/485 , H01L23/528 , H01L21/66 , H01L23/532 , H01L23/525 , H01L23/62
Abstract: A method of fabricating a contact hole and a fuse hole includes providing a dielectric layer. A conductive pad and a fuse are disposed within the dielectric layer. Then, a first mask is formed to cover the dielectric layer. Later, a first removing process is performed by taking the first mask as a mask to remove part the dielectric layer to form a first trench. The conductive pad is disposed directly under the first trench and does not expose through the first trench. Subsequently, the first mask is removed. After that, a second mask is formed to cover the dielectric layer. Then, a second removing process is performed to remove the dielectric layer directly under the first trench to form a contact hole and to remove the dielectric layer directly above the fuse by taking the second mask as a mask to form a fuse hole.
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公开(公告)号：US20190319030A1
公开(公告)日：2019-10-17
申请号：US15952182
申请日：2018-04-12
Inventor： Wen-Fu Huang , Fu-Che Lee
IPC: H01L27/108 , H01L21/02 , H01L21/311
Abstract: A method for fabricating semiconductor device includes the steps of: providing a substrate having a memory region and a logic region; forming a stack structure on the memory region and a gate structure on the logic region; forming a first cap layer on the stack structure and the gate structure; performing an oxidation process to form an oxide layer on the first cap layer; forming a second cap layer on the oxide layer; and removing part of the second cap layer, part of the oxide layer, and part of the first cap layer on the logic region to form a spacer adjacent to the gate structure.
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公开(公告)号：US10438842B2
公开(公告)日：2019-10-08
申请号：US16003126
申请日：2018-06-08
Inventor： Feng-Yi Chang , Shih-Fang Tzou , Fu-Che Lee , Hsin-Yu Chiang , Yu-Ching Chen
IPC: H01L21/4763 , H01L21/768 , H01L21/311
Abstract: A method of fabricating a contact hole includes the steps of providing a conductive line, a mask layer covering and contacting the conductive line, a high-k dielectric layer covering and contacting the mask layer, and a first silicon oxide layer covering and contacting the high-k dielectric layer, wherein the high-k dielectric layer includes a first metal oxide layer, a second metal oxide layer and a third metal oxide layer stacked from bottom to top. A dry etching process is performed to etch the first silicon oxide layer, the high-k dielectric layer, and the mask layer to expose the conductive line and form a contact hole. Finally, a wet etching process is performed to etch the first silicon oxide layer, the third metal oxide layer and the second metal oxide layer to widen the contact hole, and the first metal oxide layer remains after the wet etching process.
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公开(公告)号：US10381306B2
公开(公告)日：2019-08-13
申请号：US15856089
申请日：2017-12-28
Inventor： Feng-Yi Chang , Shih-Fang Tzou , Fu-Che Lee , Chien-Cheng Tsai , Feng-Ming Huang
IPC: H01L23/528 , H01L21/311 , H01L27/108 , H01L21/768 , H01L23/522 , H01L21/762 , H01L29/06
Abstract: A semiconductor memory device and a manufacturing method thereof are provided in the present invention. An under-cut structure is formed at an edge of a bit line contact opening in the process of forming the bit line contact opening for avoiding short problems caused by alignment shifting, and the process window of the process of forming the bit line contact opening may be improved accordingly.
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公开(公告)号：US10366889B2
公开(公告)日：2019-07-30
申请号：US15660967
申请日：2017-07-27
Inventor： Feng-Yi Chang , Fu-Che Lee , Chieh-Te Chen , Yi-Ching Chang
IPC: H01L21/033 , H01L21/3213 , H01L27/115
Abstract: A method of forming a semiconductor device includes the following steps. First of all, a material layer is formed on a substrate, and a sidewall image transferring process is performed to form plural first mask patterns on the material layer, with the first mask patterns parallel extended along a first direction. Next, a pattern splitting process is performed to remove a portion of the first mask patterns to form plural second openings, with the second openings parallel extended along a second direction, across the first mask patterns. Then, the material layer is patterned by using rest portions of the first mask patterns as a mask to form plural patterns arranged in an array.
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