公开(公告)号：US20240047266A1

公开(公告)日：2024-02-08

申请号：US17880685

申请日：2022-08-04

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chia-Liang Liao ,  Chee Hau Ng ,  Ching-Yang Wen ,  Purakh Raj Verma

IPC: H01L21/762 ,  H01L21/304 ,  H01L21/768

CPC classification number: H01L21/76251 ,  H01L21/304 ,  H01L21/76865

Abstract: A method of forming a protective layer utilized in a silicon remove process includes bonding a first wafer to a second wafer, wherein the first wafer comprises a first silicon substrate with a first device structure disposed thereon and the second wafer comprises a second silicon substrate with a second device structure disposed thereon. After that, a first trim process is performed to thin laterally an edge of the first wafer and an edge of the second device structure. After the first trim process, a protective layer is formed to cover a back side of the second silicon substrate. After forming the protective layer, a silicon remove process is performed to remove only the first silicon substrate.

公开(公告)号：US20230411343A1

公开(公告)日：2023-12-21

申请号：US17883595

申请日：2022-08-08

Applicant: United Microelectronics Corp.

Inventor： Sheng Zhang ,  Kai Zhu ,  Chien-Kee Pang ,  Chia-Liang Liao

IPC: H01L23/00 ,  H01L21/02

CPC classification number: H01L24/80 ,  H01L21/02337 ,  H01L2224/80895 ,  H01L2224/80896

Abstract: Provided is a manufacturing method of a semiconductor structure. The manufacturing method includes the following steps. A first dielectric layer is formed on a first substrate. A second dielectric layer is formed on a second substrate. A first heat treatment is performed on the first dielectric layer and the second dielectric layer, wherein a temperature of the first heat treatment is between 300° C. and 400° C. A first conductive via is formed in the first dielectric layer. A second conductive via is formed in the second dielectric layer. The first substrate and the second substrate are bonded in a manner that the first dielectric layer faces the second dielectric layer, so as to connect the first conductive via and the second conductive via.

公开(公告)号：US10658366B2

公开(公告)日：2020-05-19

申请号：US15920468

申请日：2018-03-14

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Chia-Liang Liao ,  Feng-Yi Chang ,  Fu-Che Lee ,  Chieh-Te Chen ,  Yi-Wang Zhan

IPC: H01L27/108 ,  H01L21/768 ,  H01L23/535 ,  H01L21/311 ,  H01L23/532 ,  H01L23/522

Abstract: A method for fabricating semiconductor device includes the steps of: providing a material layer having a contact pad therein; forming a dielectric layer on the material layer and the contact pad; forming a doped oxide layer on the dielectric layer; forming an oxide layer on the doped oxide layer; performing a first etching process to remove part of the oxide layer, part of the doped oxide layer, and part of the dielectric layer to form a first contact hole; performing a second etching process to remove part of the doped oxide layer to form a second contact hole; and forming a conductive layer in the second contact hole to form a contact plug.

公开(公告)号：US20200105764A1

公开(公告)日：2020-04-02

申请号：US16175858

申请日：2018-10-31

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Wei-Lun Hsu ,  Gang-Yi Lin ,  Yu-Hsiang Hung ,  Ying-Chih Lin ,  Feng-Yi Chang ,  Ming-Te Wei ,  Shih-Fang Tzou ,  Fu-Che Lee ,  Chia-Liang Liao

IPC: H01L27/108 ,  G11C11/402 ,  H01L23/538

Abstract: A method of forming a layout definition of a semiconductor device includes the following steps. Firstly, a plurality of first patterns is established to form a material layer over a substrate, with the first patterns being regularly arranged in a plurality of columns along a first direction to form an array arrangement. Next, a plurality of second patterns is established to surround the first patterns. Then, a third pattern is established to form a blocking layer on the material layer, with the third pattern being overlapped with a portion of the second patterns and with at least one of the second patterns being partially exposed from the third pattern. Finally, the first patterns are used to form a plurality of first openings in a stacked structure on the substrate to expose a portion of the substrate respectively.