公开(公告)号：US20180323227A1

公开(公告)日：2018-11-08

申请号：US15586102

申请日：2017-05-03

Applicant: United Microelectronics Corp.

Inventor： Sheng Zhang ,  Wen-Bo Ding ,  Zhi-Rui Sheng ,  Chien-En Hsu ,  Chien-Kee Pang

IPC: H01L27/146 ,  H01L21/306 ,  H01L23/00

Abstract: A wafer level packaging method includes the following steps. A first wafer is bonded over a second wafer. A first grinding process on the first wafer is performed, to remove an upper chamfered edge of the first wafer and reduce a thickness of the first wafer. A trimming process is performed on the first wafer, to remove a lower chamfered edge of the first wafer to form a trimmed first wafer. A second grinding process is performed on the trimmed first wafer, to reduce a thickness of the trimmed first wafer.

公开(公告)号：US20230094739A1

公开(公告)日：2023-03-30

申请号：US17510392

申请日：2021-10-26

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： CHUNYUAN QI ,  Sheng Zhang ,  XINGXING CHEN ,  Chien-Kee Pang

IPC: H01L29/786 ,  H01L29/10 ,  H01L29/16

Abstract: An silicon-on-insulator substrate is provided in the present invention, including a handler, a polysilicon trap-rich layer formed on the handler, an oxide layer formed on the polysilicon trap-rich layer and a monocrystalline silicon layer formed directly on the oxide layer, wherein a bonding interface is between the monocrystalline silicon layer and the oxide layer.

公开(公告)号：US20220415926A1

公开(公告)日：2022-12-29

申请号：US17383283

申请日：2021-07-22

Applicant: United Microelectronics Corp.

Inventor： Sheng Zhang ,  Chunyuan Qi ,  Xingxing Chen ,  Chien-Kee Pang

IPC: H01L27/12 ,  H01L21/762 ,  H01L21/84

Abstract: Provided are a semiconductor structure and a manufacturing method thereof. The semiconductor structure includes a carrier substrate, a trap-rich layer, a dielectric layer, an interconnect structure, a device structure layer and a circuit structure. The trap-rich layer is disposed on the carrier substrate. The dielectric layer is disposed on the trap-rich layer. The interconnect structure is disposed on the dielectric layer. The device structure layer is disposed on the interconnect structure and electrically connected to the interconnect structure. The circuit structure is disposed on the device structure layer and electrically connected to the device structure layer.

公开(公告)号：US10580823B2

公开(公告)日：2020-03-03

申请号：US15586102

申请日：2017-05-03

Applicant: United Microelectronics Corp.

Inventor： Sheng Zhang ,  Wen-Bo Ding ,  Zhi-Rui Sheng ,  Chien-En Hsu ,  Chien-Kee Pang

IPC: H01L27/146 ,  H01L23/00

Abstract: A wafer level packaging method includes the following steps. A first wafer is bonded over a second wafer. A first grinding process on the first wafer is performed, to remove an upper chamfered edge of the first wafer and reduce a thickness of the first wafer. A trimming process is performed on the first wafer, to remove a lower chamfered edge of the first wafer to form a trimmed first wafer. A second grinding process is performed on the trimmed first wafer, to reduce a thickness of the trimmed first wafer.

公开(公告)号：US09852912B1

公开(公告)日：2017-12-26

申请号：US15270638

申请日：2016-09-20

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Sheng Zhang ,  Liang Yi ,  Wen-Bo Ding ,  Chien-Kee Pang ,  Yu-Yang Chen

IPC: H01L21/4763 ,  H01L21/28 ,  H01L27/11521

CPC classification number: H01L21/28273

Abstract: A method of manufacturing a semiconductor device includes providing a silicon substrate with multiple layers formed on a front side and a backside, wherein at least a dielectric layer is formed on the backside of the silicon substrate; defining isolation regions and active regions at the front side of the silicon substrate, wherein the active regions are separated by the isolation regions; treating the multiple layers formed at the front side and the backside of the silicon substrate, so as to remain the dielectric layer as an outermost layer exposed at the backside of the silicon substrate; and depositing a polysilicon layer on the isolation regions and the active regions at the front side of the silicon substrate.

公开(公告)号：US12266578B2

公开(公告)日：2025-04-01

申请号：US17892326

申请日：2022-08-22

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Sheng Zhang ,  Chien-Kee Pang ,  Xin Zhao

IPC: H01L21/66

Abstract: A chips bonding auxiliary structure includes a first chip, an auxiliary pattern and a second chip. The first chip has a first surface. The auxiliary pattern is form on the first surface. The second chip has a second surface bonding to the first surface to form at least one gap space surrounding the auxiliary pattern.

公开(公告)号：US20230154926A1

公开(公告)日：2023-05-18

申请号：US18152781

申请日：2023-01-11

Applicant: United Microelectronics Corp.

Inventor： Sheng Zhang ,  Chunyuan QI ,  Xingxing Chen ,  Chien-Kee Pang

IPC: H01L27/12 ,  H01L21/84 ,  H01L21/762

CPC classification number: H01L27/1203 ,  H01L21/84 ,  H01L21/76256 ,  H01L21/02274

Abstract: Provided are a semiconductor structure and a manufacturing method thereof. The semiconductor structure includes a carrier substrate, a trap-rich layer, a dielectric layer, an interconnect structure, a device structure layer and a circuit structure. The trap-rich layer is disposed on the carrier substrate. The dielectric layer is disposed on the trap-rich layer. The interconnect structure is disposed on the dielectric layer. The device structure layer is disposed on the interconnect structure and electrically connected to the interconnect structure. The circuit structure is disposed on the device structure layer and electrically connected to the device structure layer.

公开(公告)号：US11456221B2

公开(公告)日：2022-09-27

申请号：US16906330

申请日：2020-06-19

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Sheng Zhang ,  Chien-Kee Pang ,  Xin Zhao

IPC: H01L21/66

Abstract: A method for measuring chips bonding strength includes steps as follows: An auxiliary pattern is formed on a first surface of a first chip. A second surface of a second chip is bonded to the first surface to form at least one gap space surrounding the auxiliary pattern. Next, dimensions of the at least one gap space and the auxiliary pattern are measure respectively; and the bonding strength between the first chip and the second chip is estimated according to the dimensions.

公开(公告)号：US20140342473A1

公开(公告)日：2014-11-20

申请号：US13894031

申请日：2013-05-14

Applicant: United Microelectronics Corp.

Inventor： Sheng Zhang ,  Guang-You Yu ,  Ying-Jie Xu ,  Chaw Che

IPC: H01L21/66

CPC classification number: H01L21/324 ,  H01L21/28185 ,  H01L21/28202 ,  H01L22/14

Abstract: A method for detecting metal contamination from a film-forming process causing interface traps is described. The film-forming process is performed to form a dielectric film on a wafer. An annealing treatment is performed to reduce the interface traps between the wafer and the dielectric film. Thereafter, the bulk recombination lifetime (BRLT) of the wafer is measured to estimate the amount of the metal contamination.

Abstract translation: 描述了一种从成膜过程引起界面陷阱中检测金属污染的方法。 进行成膜处理以在晶片上形成电介质膜。 进行退火处理以减少晶片和电介质膜之间的界面陷阱。 此后，测量晶片的体积复合寿命（BRLT）以估计金属污染的量。

公开(公告)号：US11605648B2

公开(公告)日：2023-03-14

申请号：US17383283

申请日：2021-07-22

Applicant: United Microelectronics Corp.

Inventor： Sheng Zhang ,  Chunyuan Qi ,  Xingxing Chen ,  Chien-Kee Pang

IPC: H01L27/12 ,  H01L21/84 ,  H01L21/762 ,  H01L21/02

Abstract: Provided are a semiconductor structure and a manufacturing method thereof. The semiconductor structure includes a carrier substrate, a trap-rich layer, a dielectric layer, an interconnect structure, a device structure layer and a circuit structure. The trap-rich layer is disposed on the carrier substrate. The dielectric layer is disposed on the trap-rich layer. The interconnect structure is disposed on the dielectric layer. The device structure layer is disposed on the interconnect structure and electrically connected to the interconnect structure. The circuit structure is disposed on the device structure layer and electrically connected to the device structure layer.