公开(公告)号：US20180315759A1

公开(公告)日：2018-11-01

申请号：US15920468

申请日：2018-03-14

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Chia-Liang Liao ,  Feng-Yi Chang ,  Fu-Che Lee ,  Chieh-Te Chen ,  Yi-Wang Zhan

IPC: H01L27/108 ,  H01L21/768 ,  H01L21/311 ,  H01L23/532 ,  H01L23/535

Abstract: A method for fabricating semiconductor device includes the steps of: providing a material layer having a contact pad therein; forming a dielectric layer on the material layer and the contact pad; forming a doped oxide layer on the dielectric layer; forming an oxide layer on the doped oxide layer; performing a first etching process to remove part of the oxide layer, part of the doped oxide layer, and part of the dielectric layer to form a first contact hole; performing a second etching process to remove part of the doped oxide layer to form a second contact hole; and forming a conductive layer in the second contact hole to form a contact plug.

公开(公告)号：US12080622B2

公开(公告)日：2024-09-03

申请号：US18136329

申请日：2023-04-18

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chia-Liang Liao ,  Purakh Raj Verma ,  Ching-Yang Wen ,  Chee Hau Ng

IPC: H01L23/373 ,  H01L21/48 ,  H01L23/15

CPC classification number: H01L23/3735 ,  H01L21/4871 ,  H01L23/15 ,  H01L23/3736

Abstract: A semiconductor structure includes a glass substrate and a device structure. The glass substrate includes a glass layer, a heat dissipation layer and a silicon nitride layer stacked from bottom to top. The device structure includes at least one semiconductor device integrated in a device layer situated over the silicon nitride layer of the glass substrate. Or, the glass substrate includes a glass layer and a silicon nitride layer stacked from bottom to top. The device structure includes at least one semiconductor device integrated in a device layer, and a heat dissipation layer is stacked on the device layer, wherein the heat dissipation layer is bonded with the silicon nitride layer of the glass substrate. The present invention also provides a method of wafer bonding for manufacturing said semiconductor structure.

公开(公告)号：US20220013430A1

公开(公告)日：2022-01-13

申请号：US16924206

申请日：2020-07-09

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chia-Liang Liao ,  Purakh Raj Verma ,  Ching-Yang Wen ,  Chee Hau Ng

IPC: H01L23/373 ,  H01L23/15 ,  H01L21/48

Abstract: A semiconductor structure includes a glass substrate and a device wafer. The glass substrate includes a glass layer, a heat dissipation layer and a silicon nitride layer stacked from bottom to top. The device wafer includes at least one semiconductor device integrated in a device layer situated over the silicon nitride layer of the glass substrate. Or, the glass substrate includes a glass layer and a silicon nitride layer stacked from bottom to top. The device wafer includes at least one semiconductor device integrated in a device layer, and a heat dissipation layer is stacked on the device layer, wherein the heat dissipation layer is bonded with the silicon nitride layer of the glass substrate. The present invention also provides a method of wafer bonding for manufacturing said semiconductor structure.

公开(公告)号：US20190035743A1

公开(公告)日：2019-01-31

申请号：US16003090

申请日：2018-06-07

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Feng-Yi Chang ,  Fu-Che Lee ,  Yi-Wang Zhan ,  Chia-Liang Liao ,  Yu-Cheng Tung ,  Chien-Hao Chen ,  Chia-Hung Wang

IPC: H01L23/544 ,  H01L27/108

CPC classification number: H01L23/544 ,  H01L21/31116 ,  H01L21/31144 ,  H01L27/108 ,  H01L27/10808 ,  H01L27/10852 ,  H01L2223/5442 ,  H01L2223/54426 ,  H01L2223/5446

Abstract: A semiconductor structure is disclosed. The semiconductor structure includes a substrate having a scribe line region. A material layer is formed on the scribe line region and has a rectangular region defined therein. The rectangular region has a pair of first edges parallel with a widthwise direction of the scribe line region and a pair of second edges parallel with a lengthwise direction of the scribe line region. A pair of first alignment features is formed in the material layer along the first edges, and a pair of second alignment features is formed in the material layer along the second edges. The space between the pair of first alignment features is larger than a space between the pair of the second alignment features.

公开(公告)号：US20230268246A1

公开(公告)日：2023-08-24

申请号：US18136329

申请日：2023-04-18

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chia-Liang Liao ,  Purakh Raj Verma ,  Ching-Yang Wen ,  Chee Hau Ng

IPC: H01L23/373 ,  H01L21/48 ,  H01L23/15

CPC classification number: H01L23/3735 ,  H01L21/4871 ,  H01L23/15 ,  H01L23/3736

Abstract: A semiconductor structure includes a glass substrate and a device structure. The glass substrate includes a glass layer, a heat dissipation layer and a silicon nitride layer stacked from bottom to top. The device structure includes at least one semiconductor device integrated in a device layer situated over the silicon nitride layer of the glass substrate. Or, the glass substrate includes a glass layer and a silicon nitride layer stacked from bottom to top. The device structure includes at least one semiconductor device integrated in a device layer, and a heat dissipation layer is stacked on the device layer, wherein the heat dissipation layer is bonded with the silicon nitride layer of the glass substrate. The present invention also provides a method of wafer bonding for manufacturing said semiconductor structure.

公开(公告)号：US11670567B2

公开(公告)日：2023-06-06

申请号：US16924206

申请日：2020-07-09

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chia-Liang Liao ,  Purakh Raj Verma ,  Ching-Yang Wen ,  Chee Hau Ng

IPC: H01L23/373 ,  H01L21/48 ,  H01L23/15

CPC classification number: H01L23/3735 ,  H01L21/4871 ,  H01L23/15 ,  H01L23/3736

Abstract: A semiconductor structure includes a glass substrate and a device wafer. The glass substrate includes a glass layer, a heat dissipation layer and a silicon nitride layer stacked from bottom to top. The device wafer includes at least one semiconductor device integrated in a device layer situated over the silicon nitride layer of the glass substrate. Or, the glass substrate includes a glass layer and a silicon nitride layer stacked from bottom to top. The device wafer includes at least one semiconductor device integrated in a device layer, and a heat dissipation layer is stacked on the device layer, wherein the heat dissipation layer is bonded with the silicon nitride layer of the glass substrate. The present invention also provides a method of wafer bonding for manufacturing said semiconductor structure.

公开(公告)号：US10795255B2

公开(公告)日：2020-10-06

申请号：US16175858

申请日：2018-10-31

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Wei-Lun Hsu ,  Gang-Yi Lin ,  Yu-Hsiang Hung ,  Ying-Chih Lin ,  Feng-Yi Chang ,  Ming-Te Wei ,  Shih-Fang Tzou ,  Fu-Che Lee ,  Chia-Liang Liao

IPC: G03F1/36 ,  H01L23/538 ,  G03F1/38 ,  H01L21/033 ,  H01L21/308 ,  G03F1/00 ,  G03F7/20 ,  G03F7/00 ,  H01L27/108

Abstract: A method of forming a layout definition of a semiconductor device includes the following steps. Firstly, a plurality of first patterns is established to form a material layer over a substrate, with the first patterns being regularly arranged in a plurality of columns along a first direction to form an array arrangement. Next, a plurality of second patterns is established to surround the first patterns. Then, a third pattern is established to form a blocking layer on the material layer, with the third pattern being overlapped with a portion of the second patterns and with at least one of the second patterns being partially exposed from the third pattern. Finally, the first patterns are used to form a plurality of first openings in a stacked structure on the substrate to expose a portion of the substrate respectively.

公开(公告)号：US10535610B2

公开(公告)日：2020-01-14

申请号：US16003090

申请日：2018-06-07

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Feng-Yi Chang ,  Fu-Che Lee ,  Yi-Wang Zhan ,  Chia-Liang Liao ,  Yu-Cheng Tung ,  Chien-Hao Chen ,  Chia-Hung Wang

IPC: H01L23/544 ,  H01L27/108 ,  H01L21/311

Abstract: A semiconductor structure is disclosed. The semiconductor structure includes a substrate having a scribe line region. A material layer is formed on the scribe line region and has a rectangular region defined therein. The rectangular region has a pair of first edges parallel with a widthwise direction of the scribe line region and a pair of second edges parallel with a lengthwise direction of the scribe line region. A pair of first alignment features is formed in the material layer along the first edges, and a pair of second alignment features is formed in the material layer along the second edges. The space between the pair of first alignment features is larger than a space between the pair of the second alignment features.

公开(公告)号：US12278210B2

公开(公告)日：2025-04-15

申请号：US17883595

申请日：2022-08-08

Applicant: United Microelectronics Corp.

Inventor： Sheng Zhang ,  Kai Zhu ,  Chien-Kee Pang ,  Chia-Liang Liao

IPC: H01L21/00 ,  H01L21/02 ,  H01L23/00

Abstract: Provided is a manufacturing method of a semiconductor structure. The manufacturing method includes the following steps. A first dielectric layer is formed on a first substrate. A second dielectric layer is formed on a second substrate. A first heat treatment is performed on the first dielectric layer and the second dielectric layer, wherein a temperature of the first heat treatment is between 300° C. and 400° C. A first conductive via is formed in the first dielectric layer. A second conductive via is formed in the second dielectric layer. The first substrate and the second substrate are bonded in a manner that the first dielectric layer faces the second dielectric layer, so as to connect the first conductive via and the second conductive via.

公开(公告)号：US20240047266A1

公开(公告)日：2024-02-08

申请号：US17880685

申请日：2022-08-04

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chia-Liang Liao ,  Chee Hau Ng ,  Ching-Yang Wen ,  Purakh Raj Verma

IPC: H01L21/762 ,  H01L21/304 ,  H01L21/768

CPC classification number: H01L21/76251 ,  H01L21/304 ,  H01L21/76865

Abstract: A method of forming a protective layer utilized in a silicon remove process includes bonding a first wafer to a second wafer, wherein the first wafer comprises a first silicon substrate with a first device structure disposed thereon and the second wafer comprises a second silicon substrate with a second device structure disposed thereon. After that, a first trim process is performed to thin laterally an edge of the first wafer and an edge of the second device structure. After the first trim process, a protective layer is formed to cover a back side of the second silicon substrate. After forming the protective layer, a silicon remove process is performed to remove only the first silicon substrate.