公开(公告)号：US11735260B2

公开(公告)日：2023-08-22

申请号：US16184961

申请日：2018-11-08

Applicant: Winbond Electronics Corp.

Inventor： Yasuhiro Tomita

IPC: G11C13/04 ,  G11C13/00

CPC classification number: G11C13/0069 ,  G11C13/003 ,  G11C13/004 ,  G11C13/0023 ,  G11C13/0033 ,  G11C13/0035 ,  G11C2013/0083 ,  G11C2013/0092 ,  G11C2211/5641 ,  G11C2211/5646 ,  G11C2213/79 ,  G11C2213/82

Abstract: A semiconductor memory device capable of satisfying multiple reliability conditions and multiple performance requirements is provided. A variable resistance memory of the disclosure makes it possible to write data in a memory array by changing a write condition according to the type of a write command from the outside. If the write command is an endurance-related command, an endurance algorithm is selected and data is written in an endurance storage area. If the write command is a retention-related command, a retention algorithm is selected and data is written in a retention storage area.

公开(公告)号：US11257865B2

公开(公告)日：2022-02-22

申请号：US16591944

申请日：2019-10-03

Applicant: Winbond Electronics Corp.

Inventor： Yasuhiro Tomita ,  Chi Shun Lin

IPC: H01L27/24 ,  H01L23/528 ,  H01L23/522 ,  H01L45/00 ,  G11C13/00

Abstract: The invention provides a resistive memory with better area efficiency without degrading reliability, which includes an array area, word lines, a local bit line, source lines, and a shared bit line. In the array area, memory cells are arranged in a matrix, and each memory cells includes a variable resistance element and an accessing transistor. The word lines extend in a row direction of the array area and are connected to the memory cells in the row direction. The local bit line extends in a column direction of the array area. The source lines extend in the column direction and are connected to first electrodes of the memory cells in the column direction. The shared bit line is connected to the local bit line. The shared bit line extends in the row direction and is connected to second electrodes of the memory cells in the row direction.

公开(公告)号：US20220013172A1

公开(公告)日：2022-01-13

申请号：US17367641

申请日：2021-07-06

Applicant: Winbond Electronics Corp.

Inventor： Yasuhiro Tomita ,  Masaru Yano

IPC: G11C13/00 ,  G11C11/54

Abstract: A crossbar array apparatus suppressing deterioration of write precision due to a sneak current is provided. A synapse array apparatus includes a crossbar array configured by connecting resistance-variable type memory elements, a row selecting/driving circuit, a column selecting/driving circuit, and a writing unit performing a write operation to a selected resistance-variable type memory element. The writing unit measures the sneak current generated when applying a write voltage to a selected row line before applying the write voltage, and then the writing unit performs the write operation to the selected resistance-variable type memory element by applying a write voltage having a sum of the measured sneak current and a current generated for performing the write operation.

公开(公告)号：US11222923B2

公开(公告)日：2022-01-11

申请号：US16666421

申请日：2019-10-29

Applicant: Winbond Electronics Corp.

Inventor： Yasuhiro Tomita

IPC: H01L27/24 ,  H01L45/00 ,  G11C13/00

Abstract: The disclosure provides a resistance variable memory that can realize high integration. The resistance variable memory of the disclosure includes a plurality of transistors formed on a surface of a substrate, and a plurality of variable resistance elements stacked on the surface of the substrate in a vertical direction. One electrode of each of the variable resistance elements is commonly electrically connected to one electrode of one transistor, and another electrode of each of the variable resistance elements is respectively electrically connected to a bit line, and another electrode of each of the transistors is electrically connected to a source line, and each gate of transistors in a row direction is commonly connected to a word line.

公开(公告)号：US20190244663A1

公开(公告)日：2019-08-08

申请号：US16184961

申请日：2018-11-08

Applicant: Winbond Electronics Corp.

Inventor： Yasuhiro Tomita

IPC: G11C13/00

CPC classification number: G11C13/0069 ,  G11C13/0033 ,  G11C13/004 ,  G11C2013/0092

Abstract: A semiconductor memory device capable of satisfying multiple reliability conditions and multiple performance requirements is provided. A variable resistance memory of the disclosure makes it possible to write data in a memory array by changing a write condition according to the type of a write command from the outside. If the write command is an endurance-related command, an endurance algorithm is selected and data is written in an endurance storage area. If the write command is a retention-related command, a retention algorithm is selected and data is written in a retention storage area.