公开(公告)号：US10483996B1

公开(公告)日：2019-11-19

申请号：US15991539

申请日：2018-05-29

Applicant: Xilinx, Inc.

Inventor： Christophe Erdmann ,  Bob W. Verbruggen ,  Ali Boumaalif ,  Bruno Miguel Vaz

IPC: H03M1/12 ,  G06F1/10 ,  H03M1/66 ,  H03M1/06

Abstract: Apparatus and associated methods relate to modulating polarity on sample outputs from a time-interleaved analog-to-digital converter (TIADC) as an input to a time skew extractor in a clock skew calibration control loop. In an illustrative example, a multiplier-mixer may impart a polarity change to every other data sample transmitted between the TIADC and the time skew extractor. In some examples, a multiplexer may select between the polarity modulated samples and non-polarity modulated samples before the multiplier-mixer. Selection between the polarity modulated samples and the non-polarity modulated samples may be based on, for example, determination of specific frequency bands of an analog input signal. Various embodiments may improve convergence of clock skew calibration control loops for analog input signals sampled with a TIADC near a Nyquist frequency.

公开(公告)号：US10379570B1

公开(公告)日：2019-08-13

申请号：US15989619

申请日：2018-05-25

Applicant: Xilinx, Inc.

Inventor： Conrado K. Mesadri ,  Bob W. Verbruggen

IPC: H03B19/00 ,  G06F1/08 ,  H03K5/15 ,  G06F1/10

Abstract: A clock divider circuit receives an input clock signal having a first frequency (f) and generates an output signal having a frequency equal to f/N, where N is an odd integer. The clock divider circuit includes an edge counter to count a number of consecutive edges of the input clock signal having a first plurality, and to assert a control signal when a threshold number (N) of consecutive edges has been counted. The clock divider circuit also includes a frequency multiplier to generate an intermediate clock signal having a frequency equal to 2f/N by doubling the frequency of the control signal based at least in part on transitions of the input clock signal, and a frequency divider to generate an output clock signal having a frequency equal to f/N by halving the frequency of the intermediate clock signal.

公开(公告)号：US10298248B1

公开(公告)日：2019-05-21

申请号：US15912318

申请日：2018-03-05

Applicant: Xilinx, Inc.

Inventor： Bruno Miguel Vaz ,  Christophe Erdmann ,  Bob W. Verbruggen ,  John E. McGrath ,  Ali Boumaalif

IPC: H03M1/10 ,  H03M1/12 ,  H03K19/177

Abstract: An example apparatus for analog-to-digital conversion includes a plurality of channels each including an analog-to-digital converter (ADC), a switch configured to couple a differential input to the ADC, a first offset calibration circuit coupled to an output of the ADC, a multiplier coupled to an output of the first offset calibration circuit, a second offset calibration circuit coupled to an output of the multiplier, and a pseudorandom bit sequence (PRBS) generator coupled to the switch and the multiplier. The apparatus further includes a gain calibration circuit coupled to an output of the second offset calibration circuit in each of the plurality of channels; and a time-skew calibration circuit coupled to an output of the gain calibration circuit.

公开(公告)号：US10291247B1

公开(公告)日：2019-05-14

申请号：US15914364

申请日：2018-03-07

Applicant: Xilinx, Inc.

Inventor： Bob W. Verbruggen ,  Christophe Erdmann ,  Bruno Miguel Vaz

IPC: H03M1/06 ,  H03M1/10 ,  H03M1/12

Abstract: An example time-skew calibration circuit includes a plurality of first circuits, each including a first accumulator and a second accumulator. The time-skew calibration circuit further includes a plurality of second circuits, each including a first adder coupled to outputs of the first accumulator and the second accumulator, and a first subtractor coupled to the outputs of the first accumulator and the second accumulator. The time-skew calibration circuit further includes a decision circuit configured to combine an output of the first adder and an output of the first subtractor.

公开(公告)号：US20190115926A1

公开(公告)日：2019-04-18

申请号：US15784022

申请日：2017-10-13

Applicant: Xilinx, Inc.

Inventor： Augusto R. Ximenes ,  Bob W. Verbruggen ,  Christophe Erdmann

IPC: H03L7/091 ,  H03L7/099

Abstract: An example digital-to-time converter (DTC) includes: a delay chain circuit having a plurality of delay cells coupled in sequence, the delay chain circuit including a first input to receive a first clock signal and a second input to receive a second clock signal; and a DEM controller coupled to the delay chain circuit to provide a plurality of control signals to the plurality of delay cells, respectively.