公开(公告)号：US10917077B1

公开(公告)日：2021-02-09

申请号：US16694485

申请日：2019-11-25

Applicant: Xilinx, Inc.

Inventor： Ali Boumaalif ,  John E. McGrath

IPC: G06F1/03 ,  H03C3/00 ,  H03K5/00 ,  H03K4/08

Abstract: A device includes a plurality of phase accumulators, a multiplexer, and an oscillator. The plurality of phase accumulators is configured to receive a plurality of frequencies and generate a plurality of ramp signals. The multiplexer is configured to receive the plurality of ramp signals from the plurality of phase accumulators and to select one ramp signal from the plurality of ramp signals. The oscillator is configured to receive the one selected ramp signal and to generate one amplitude signal associated therewith. The plurality of phase accumulators continues generating their respective ramp signal. The multiplexer subsequent to selecting the one ramp signal is configured to select another ramp signal associated with another one phase accumulator of the plurality of phase accumulators. The oscillator is further configured to receive the selected another ramp signal and to generate another amplitude signal associated therewith.

公开(公告)号：US10476514B1

公开(公告)日：2019-11-12

申请号：US15992797

申请日：2018-05-30

Applicant: Xilinx, Inc.

Inventor： Bruno Miguel Vaz ,  John E. McGrath ,  Conrado K. Mesadri ,  Woon C. Wong ,  Ali Boumaalif ,  Christophe Erdmann ,  Brendan Farley

IPC: H03M1/12 ,  G01R31/3185 ,  H03M1/10 ,  H04L12/43 ,  H04L12/433

Abstract: An integrated circuit is described. The integrated circuit comprises a first portion having programmable resources; a second portion having hardened circuits including an analog-to-digital converter circuit configured to receive an input signal and generate an output signal; and a monitor circuit configured to receive an output signal generated by the analog-to-digital converter circuit; wherein the monitor circuit is configurable to control a calibration of the analog-to-digital converter circuit based upon signal characteristics of the output signal generated by the analog-to-digital converter circuit. A method of receiving data in an integrated circuit is also described.

公开(公告)号：US10826517B1

公开(公告)日：2020-11-03

申请号：US16680356

申请日：2019-11-11

Applicant: Xilinx, Inc.

Inventor： Bruno Miguel Vaz ,  John E. McGrath ,  Conrado K. Mesadri ,  Woon C. Wong ,  Ali Boumaalif ,  Christopher Erdman ,  Brendan Farley

IPC: H03M1/12 ,  H03M1/10 ,  G01R31/3185 ,  H04L12/43 ,  H04L12/433

Abstract: An integrated circuit is described. The integrated circuit comprises an analog-to-digital converter circuit configured to receive an input signal at an input and generate an output signal at an output; and a monitor circuit coupled to the output of the analog-to-digital converter circuit, the monitor circuit configured to receive the output signal and to generate integration coefficients for the analog-to-digital converter circuit; wherein the integration coefficients are dynamically generated based upon signal characteristics of the output signal generated by the analog-to-digital converter circuit. A method of receiving data in an integrated circuit is also described.

公开(公告)号：US10483996B1

公开(公告)日：2019-11-19

申请号：US15991539

申请日：2018-05-29

Applicant: Xilinx, Inc.

Inventor： Christophe Erdmann ,  Bob W. Verbruggen ,  Ali Boumaalif ,  Bruno Miguel Vaz

IPC: H03M1/12 ,  G06F1/10 ,  H03M1/66 ,  H03M1/06

Abstract: Apparatus and associated methods relate to modulating polarity on sample outputs from a time-interleaved analog-to-digital converter (TIADC) as an input to a time skew extractor in a clock skew calibration control loop. In an illustrative example, a multiplier-mixer may impart a polarity change to every other data sample transmitted between the TIADC and the time skew extractor. In some examples, a multiplexer may select between the polarity modulated samples and non-polarity modulated samples before the multiplier-mixer. Selection between the polarity modulated samples and the non-polarity modulated samples may be based on, for example, determination of specific frequency bands of an analog input signal. Various embodiments may improve convergence of clock skew calibration control loops for analog input signals sampled with a TIADC near a Nyquist frequency.

公开(公告)号：US10298248B1

公开(公告)日：2019-05-21

申请号：US15912318

申请日：2018-03-05

Applicant: Xilinx, Inc.

Inventor： Bruno Miguel Vaz ,  Christophe Erdmann ,  Bob W. Verbruggen ,  John E. McGrath ,  Ali Boumaalif

IPC: H03M1/10 ,  H03M1/12 ,  H03K19/177

Abstract: An example apparatus for analog-to-digital conversion includes a plurality of channels each including an analog-to-digital converter (ADC), a switch configured to couple a differential input to the ADC, a first offset calibration circuit coupled to an output of the ADC, a multiplier coupled to an output of the first offset calibration circuit, a second offset calibration circuit coupled to an output of the multiplier, and a pseudorandom bit sequence (PRBS) generator coupled to the switch and the multiplier. The apparatus further includes a gain calibration circuit coupled to an output of the second offset calibration circuit in each of the plurality of channels; and a time-skew calibration circuit coupled to an output of the gain calibration circuit.