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公开(公告)号：US10886906B1
公开(公告)日：2021-01-05
申请号：US15989623
申请日：2018-05-25
申请人： Xilinx, Inc.
摘要： A duty-cycle adjustment circuit receives a differential pair of input signals and generates an output signal based on the differential pair. The duty-cycle adjustment circuit drives the output signal to a logic-high state based on transitions of a first polarity in a first input signal of the differential pair, and drives the output signal to a logic-low state based on transitions of the first polarity in a second input signal of the differential pair. For example, rising-edge transitions of the output signal may be aligned with rising-edge transitions of the first input signal, and falling-edge transitions of the output signal may be aligned with rising-edge transitions of the second input signal. Alternatively, rising-edge transitions of the output signal may be aligned with falling-edge transitions of the first input signal, and falling-edge transitions of the output signal may be aligned with falling-edge transitions of the second input signal.
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公开(公告)号：US09419636B1
公开(公告)日：2016-08-16
申请号：US14682868
申请日：2015-04-09
申请人： Xilinx, Inc.
CPC分类号： H03M1/66 , H03M1/0836 , H03M1/747
摘要： In one example, a current steering circuit includes an output transistor pair responsive to a first gate bias voltage. The current steering circuit further includes a first switch comprising a first source-coupled transistor pair coupled to the output transistor pair and responsive to a first differential gate voltage, and a second switch comprising a second source-coupled transistor pair coupled to the output transistor pair and responsive to a second differential gate voltage. The current steering circuit further includes a current source configured to source a bias current. The current steering circuit further includes a third switch comprising a third source-coupled transistor pair coupled between the current source and each of the first switch and the second switch, the third source-coupled transistor pair responsive to a third differential gate voltage.
摘要翻译： 在一个示例中，电流控制电路包括响应于第一栅极偏置电压的输出晶体管对。 电流转向电路还包括第一开关，其包括耦合到输出晶体管对并响应于第一差分栅极电压的第一源极耦合晶体管对，以及包括耦合到输出晶体管对的第二源极耦合晶体管对的第二开关 并响应于第二差分栅极电压。 电流转向电路还包括被配置为馈送偏置电流的电流源。 电流转向电路还包括第三开关，其包括耦合在电流源与第一开关和第二开关中的每一个之间的第三源极耦合晶体管对，第三源极耦合晶体管对响应第三差分栅极电压。
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公开(公告)号：US10476514B1
公开(公告)日：2019-11-12
申请号：US15992797
申请日：2018-05-30
申请人： Xilinx, Inc.
发明人： Bruno Miguel Vaz , John E. McGrath , Conrado K. Mesadri , Woon C. Wong , Ali Boumaalif , Christophe Erdmann , Brendan Farley
IPC分类号： H03M1/12 , G01R31/3185 , H03M1/10 , H04L12/43 , H04L12/433
摘要： An integrated circuit is described. The integrated circuit comprises a first portion having programmable resources; a second portion having hardened circuits including an analog-to-digital converter circuit configured to receive an input signal and generate an output signal; and a monitor circuit configured to receive an output signal generated by the analog-to-digital converter circuit; wherein the monitor circuit is configurable to control a calibration of the analog-to-digital converter circuit based upon signal characteristics of the output signal generated by the analog-to-digital converter circuit. A method of receiving data in an integrated circuit is also described.
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公开(公告)号：US10826517B1
公开(公告)日：2020-11-03
申请号：US16680356
申请日：2019-11-11
申请人： Xilinx, Inc.
发明人： Bruno Miguel Vaz , John E. McGrath , Conrado K. Mesadri , Woon C. Wong , Ali Boumaalif , Christopher Erdman , Brendan Farley
IPC分类号： H03M1/12 , H03M1/10 , G01R31/3185 , H04L12/43 , H04L12/433
摘要： An integrated circuit is described. The integrated circuit comprises an analog-to-digital converter circuit configured to receive an input signal at an input and generate an output signal at an output; and a monitor circuit coupled to the output of the analog-to-digital converter circuit, the monitor circuit configured to receive the output signal and to generate integration coefficients for the analog-to-digital converter circuit; wherein the integration coefficients are dynamically generated based upon signal characteristics of the output signal generated by the analog-to-digital converter circuit. A method of receiving data in an integrated circuit is also described.
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公开(公告)号：US10379570B1
公开(公告)日：2019-08-13
申请号：US15989619
申请日：2018-05-25
申请人： Xilinx, Inc.
摘要： A clock divider circuit receives an input clock signal having a first frequency (f) and generates an output signal having a frequency equal to f/N, where N is an odd integer. The clock divider circuit includes an edge counter to count a number of consecutive edges of the input clock signal having a first plurality, and to assert a control signal when a threshold number (N) of consecutive edges has been counted. The clock divider circuit also includes a frequency multiplier to generate an intermediate clock signal having a frequency equal to 2f/N by doubling the frequency of the control signal based at least in part on transitions of the input clock signal, and a frequency divider to generate an output clock signal having a frequency equal to f/N by halving the frequency of the intermediate clock signal.
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