公开(公告)号：US10411656B1

公开(公告)日：2019-09-10

申请号：US16142893

申请日：2018-09-26

Applicant: Xilinx, Inc.

Inventor： Christopher H. Dick ,  Hongzhi Zhao ,  Hemang M. Parekh ,  Xiaohan Chen

IPC: H03F1/32 ,  H04L27/26 ,  H04B1/04 ,  H04N5/38 ,  H04L27/08

Abstract: A crest factor reduction (CFR) system includes a digital tilt filter coupled to an input of the CFR system. In some embodiments, the digital tilt filter is configured to receive a system input signal and generate a digital tilt filter output signal at a digital tilt filter output. In some examples, the CFR system further includes a CFR module coupled to the digital tilt filter output, where the CFR module is configured receive the digital tilt filter output signal and perform a CFR process to the digital tilt filter output signal to generate a CFR module output signal at a CFR module output. In addition, the CFR system may include a digital tilt equalizer coupled to the CFR module output, where the digital tilt equalizer is configured to receive the CFR module output signal and generate a system output signal.

公开(公告)号：US20170005627A1

公开(公告)日：2017-01-05

申请号：US14790364

申请日：2015-07-02

Applicant: Xilinx, Inc.

Inventor： Hongzhi Zhao ,  Christopher H. Dick

IPC: H03F1/32 ,  H03F3/24 ,  H04B1/04 ,  H03F3/189

CPC classification number: H03F1/3247 ,  H03F1/3252 ,  H03F1/3258 ,  H03F3/189 ,  H03F3/195 ,  H03F3/24 ,  H03F3/245 ,  H03F2201/3209 ,  H03F2201/3215 ,  H03F2201/3224 ,  H03F2201/3233 ,  H04B1/0475 ,  H04B2001/0425

Abstract: An apparatus relates generally to preconditioning an input signal. In this apparatus, a first digital predistortion module and a second digital predistortion module are for receiving the input signal for respectively providing a first predistorted signal and a second predistorted signal. A combiner is for combining the first predistorted signal and the second predistorted signal for providing an output signal. The first digital predistortion module includes a moving mean block for receiving the input signal for providing a moving mean signal. The first digital predistortion module further includes a digital predistorter for receiving the input signal and the moving mean signal for providing the first predistorted signal.

Abstract translation: 装置一般涉及预处理输入信号。 在该装置中，第一数字预失真模块和第二数字预失真模块用于接收用于分别提供第一预失真信号和第二预失真信号的输入信号。 组合器用于组合第一预失真信号和第二预失真信号以提供输出信号。 第一数字预失真模块包括移动平均块，用于接收用于提供移动平均信号的输入信号。 第一数字预失真模块还包括用于接收输入信号的数字预失真器和用于提供第一预失真信号的移动平均信号。

公开(公告)号：US11984919B2

公开(公告)日：2024-05-14

申请号：US17959079

申请日：2022-10-03

Applicant: XILINX, INC.

Inventor： Hongzhi Zhao ,  Christophe Erdmann ,  Hemang M. Parekh ,  Xing Zhao ,  Xiaohan Chen

IPC: H04B1/12 ,  H04L27/01

CPC classification number: H04B1/123 ,  H04L27/01

Abstract: Embodiments herein describe a PIM correction circuit. In a base station, TX and RX RF changes, band pass filters, duplexers, and diplexers can have severe memory effects due to their sharp transition bandwidth from pass band to stop band. PIM interference, generated by the TX signals and reflected onto the RX RF chain will include these memory effects. These memory effects make PIM cancellation complex, requiring complicated computations and circuits. However, the embodiments herein use a PIM correction circuit that separates the memory effects of the TX and RX paths from the memory effects of PIM, thereby reducing PIM cancellation complexity and hardware implementation cost.

公开(公告)号：US20230046588A1

公开(公告)日：2023-02-16

申请号：US17402892

申请日：2021-08-16

Applicant: Xilinx, Inc.

Inventor： Hongzhi Zhao ,  Xing Zhao ,  Vincent C. Barnes ,  Xiaohan Chen ,  Hemang M. Parekh

IPC: H03F1/32 ,  H03G1/00 ,  H03F3/21

Abstract: A digital predistortion (DPD) system includes an input configured to receive an input signal. In some examples, a first signal path configured to generate a first signal based on the input signal. In some examples, an error model provider configured to generate an error model signal modeled after a gate bias error voltage associated with the DPD system. In some examples, a first combiner configured to combine the first signal and the error model signal to generate a first intermediate signal, and the DPD system generates an output signal based at least on the first intermediate signal.

公开(公告)号：US11563453B1

公开(公告)日：2023-01-24

申请号：US17239395

申请日：2021-04-23

Applicant: XILINX, INC.

Inventor： Hongzhi Zhao ,  Vincent C. Barnes ,  Xiaohan Chen ,  Hemang M. Parekh

IPC: H04B1/04 ,  H03F1/32

Abstract: A transmitter for a communication system comprises a digital pre-distortion (DPD) circuit and adaptation circuitry. The DPD circuit is configured to generate a digital intermediate signal by compensating an input signal for distortions resulting from an amplifier. The amplifier is configured to output an output signal based on the digital intermediate signal. The DPD circuit includes one or more an infinite impulse response (IIR) filters configured to implement a first transfer function based on a first parameter, and a second transfer function based on the first parameter and a time constant. The DPD circuit is configured to generate an adjustment signal based on the first transfer function and the second transfer function. The adaptation circuitry is configured to update the first parameter based on the adjustment signal, the input signal, and the output signal.

公开(公告)号：US11483018B1

公开(公告)日：2022-10-25

申请号：US17339241

申请日：2021-06-04

Applicant: XILINX, INC.

Inventor： Xiaohan Chen ,  Hemang M. Parekh ,  John Edward McGrath ,  Hongzhi Zhao ,  David Eugene Melinn

IPC: H04B1/04

Abstract: Examples described herein provide a radio frequency circuit. The radio frequency circuit includes a controller; a parameter estimator circuit; a capture circuit; and a pre-distorter circuit. The pre-distorter generally includes one or more nonlinear filter circuits and configurable hardware circuitry. Each of the one or more the nonlinear filter circuits includes: adder(s); multiplier(s); and memories coupled to at least one of the adder(s) and the multiplier(s); where the configurable hardware circuitry is configured to distort one or more input signals by directing the one or more input signals along a path through the one or more adders, the one or more multipliers, and the one or more memories and by distorting the one or input signals using the nonlinear parameters stored in the one or more memories as the one or more input signals travels the path.

公开(公告)号：US09455760B1

公开(公告)日：2016-09-27

申请号：US14791096

申请日：2015-07-02

Applicant: Xilinx, Inc.

Inventor： Christopher H. Dick ,  Hemang M. Parekh ,  Hongzhi Zhao ,  Vincent C. Barnes

IPC: H04B1/04 ,  H04B1/62

CPC classification number: H04B1/62 ,  H03F1/3247 ,  H03F3/245 ,  H03F2201/3233 ,  H04B1/0475 ,  H04B2001/0425 ,  H04L25/03343 ,  H04L27/368

Abstract: Apparatus, method therefor, generally related to signal preconditioning. In such an apparatus, a signal classifier block and a delay block are commonly coupled for receiving an input signal. The delay block is for providing a delayed version of the input signal. The signal classifier block is for classifying the input signal and generating a configuration signal having configuration information for digital predistortion (“DPD”) engine parameterization in response to the input signal classification. A DPD engine is for receiving the delayed version of the input signal and the configuration signal and for providing a predistorted output signal.

Abstract translation: 装置及其方法一般与信号预处理有关。 在这种装置中，信号分类器块和延迟块通常被耦合用于接收输入信号。 延迟块用于提供输入信号的延迟版本。 信号分类器块用于对输入信号进行分类，并产生具有响应于输入信号分类的用于数字预失真（“DPD”）引擎参数化的配置信息的配置信号。 DPD引擎用于接收输入信号和配置信号的延迟版本并提供预失真的输出信号。