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公开(公告)号：US11693777B2
公开(公告)日：2023-07-04
申请号：US17493694
申请日：2021-10-04
Applicant: Xilinx, Inc.
Inventor： Steven L. Pope , Dmitri Kitariev , David J. Riddoch , Derek Roberts , Neil Turton
IPC: G06F12/0831 , G06F9/38 , G06F12/0888 , G06F13/28
CPC classification number: G06F12/0835 , G06F9/3802 , G06F12/0888 , G06F13/28
Abstract: A network interface device comprises a programmable interface configured to provide a device interface with at least one bus between the network interface device and a host device. The programmable interface is programmable to support a plurality of different types of a device interface.
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公开(公告)号：US20220400147A1
公开(公告)日：2022-12-15
申请号：US17867656
申请日：2022-07-18
Applicant: Xilinx, Inc.
Inventor： Steven L. Pope , Derek Roberts , David J. Riddoch
Abstract: A network interface device having an FPGA for providing an FPGA application. A first interface between a host computing device and the FPGA application is provided, allowing the FPGA application to make use of data-path operations provided by a transport engine on the network interface device, as well as communicate with the host. The FPGA application sends and receives data with the host via a memory that is memory mapped to a shared memory location in the host computing device, whilst the transport engine sends and receives data packets with the host via a second memory. A second interface is provided to interface the FPGA application and transport engine with the network, wherein the second interface is configured to back-pressure the transport engine.
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公开(公告)号：US11502845B2
公开(公告)日：2022-11-15
申请号：US16921590
申请日：2020-07-06
Applicant: Xilinx, Inc.
Inventor： Steven L. Pope , David J. Riddoch , Paul Fox
Abstract: A network interface device comprises an integrated circuit device comprises at least one processor. A network interface device comprises a memory. The integrated device is configured to execute a function with respect to at least a part of stored data in said memory.
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公开(公告)号：US11409569B2
公开(公告)日：2022-08-09
申请号：US15940837
申请日：2018-03-29
Applicant: XILINX, INC.
Inventor： Steven L. Pope , David J. Riddoch , Derek Roberts
Abstract: A data processing system being configured to select between different hardware resources for the running of an application configured for the sending and receiving of data over a network. The selection of hardware resources may be between resources on the network interface device, and hardware resources on the host. The selection of hardware resources may be between first and second hardware resources on the network interface device. An API is provided in the data processing system that responds to requests from the application irrespective of the hardware on which the application is executing.
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公开(公告)号：US11165683B2
公开(公告)日：2021-11-02
申请号：US15385644
申请日：2016-12-20
Applicant: XILINX, INC.
Inventor： Steven L. Pope , David J. Riddoch , Derek Roberts
IPC: H04L12/835 , H04L12/801 , H04L12/26 , G06F13/38 , G06F15/167 , H04L12/823 , H04L12/825
Abstract: A network interface device, said network interface device has a data transmission path configured to receive data for transmission. The data for transmission is to be sent over a network by the network interface device. A monitor is configured to monitor the data transmission path to determine if an underrun condition is associated with the data transmission path. If so, an indication is included in the transmitted data packet.
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Patent Agency Ranking
公开(公告)号：US11132317B2
公开(公告)日：2021-09-28
申请号：US16782023
申请日：2020-02-04
Applicant: Xilinx, Inc.
Inventor： Steven L. Pope
IPC: H04L12/863 , H04L12/725 , G06F13/362 , G06F13/38 , G06F13/42 , G06Q40/04 , G06F15/16 , G06F15/173 , G06F13/28 , H04L12/861 , G06F13/10
Abstract: A data processing system comprising: a host computer system supporting a software entity and a receive queue for the software entity; a network interface device having a controller unit configured to provide a data port for receiving data packets from a network and a data bus interface for connection to a host computer system, the network interface device being connected to the host computer system by means of the data bus interface; and an accelerator module arranged between the controller unit and a network and having a first medium access controller for connection to the network and a second medium access controller coupled to the data port of the controller unit, the accelerator module being configured to: on behalf of the software entity, process incoming data packets received from the network in one or more streams associated with a first set of one or more network endpoints; encapsulate data resulting from said processing in network data packets directed to the software entity; and deliver the network data packets to the data port of the controller unit so as to cause the network data packets to be written to the receive queue of the software entity.
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公开(公告)号：US10999303B2
公开(公告)日：2021-05-04
申请号：US15476456
申请日：2017-03-31
Applicant: XILINX, INC.
Inventor： Steven L. Pope , David J. Riddoch , Derek Roberts
Abstract: A data analytical engine receives packets from a number of different network interface devices. The data is a replica of part or all of transmit or receive packets processed in the network interface device. A learning algorithm is applied to data from said different network interface devices and it is determined if an alert is to be generated.
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公开(公告)号：US20200274921A1
公开(公告)日：2020-08-27
申请号：US16874594
申请日：2020-05-14
Applicant: Xilinx, Inc.
Inventor： Steven L. Pope , Derek Roberts , David J. Riddoch
IPC: H04L29/08 , H04L12/721 , H04L29/06 , G06F9/50 , H04L12/935
Abstract: A network interface device having an FPGA for providing an FPGA application. A first interface between a host computing device and the FPGA application is provided, allowing the FPGA application to make use of data-path operations provided by a transport engine on the network interface device, as well as communicate with the host. The FPGA application sends and receives data with the host via a memory that is memory mapped to a shared memory location in the host computing device, whilst the transport engine sends and receives data packets with the host via a second memory. A second interface is provided to interface the FPGA application and transport engine with the network, wherein the second interface is configured to back-pressure the transport engine.
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公开(公告)号：US10733167B2
公开(公告)日：2020-08-04
申请号：US14752472
申请日：2015-06-26
Applicant: XILINX, INC.
Inventor： Steven L. Pope , David J. Riddoch , Matthew Knight
Abstract: A system has data capture devices collecting data from different points in a network. The captured data is written to a data store and is directed to an output. The data from the different data capture devices can be delivered to a data analytics device. As long as the data analytics device is able to keep pace with the data that is directed to the output, that data is used by the analytics device. If the analytics device is not able to keep pace, the data written to the data store is retrieved and is used until the analytics device has caught up.
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公开(公告)号：US10671458B2
公开(公告)日：2020-06-02
申请号：US15042507
申请日：2016-02-12
Applicant: XILINX, INC.
Inventor： Steven L. Pope , David J. Riddoch
Abstract: A method for managing I/O event notifications in a data processing system comprising a plurality of applications and an operating system having a kernel and an I/O event notification mechanism operable to maintain a plurality of I/O event notification objects each handling a set of file descriptors associated with one or more I/O resources. For each of a plurality of application-level configuration calls: intercepting at a user-level interface a configuration call from an application to the I/O event notification mechanism for configuring an I/O event notification object; and storing a set of parameters of the configuration call at a data structure, each set of parameters representing an operation on the set of file descriptors handled by the I/O event notification object; and subsequently, upon meeting a predetermined criterion: the user-level interface causing the plurality of configuration calls to be effected by means of a first system call to the kernel.
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