公开(公告)号：US09165023B2

公开(公告)日：2015-10-20

申请号：US13978251

申请日：2011-01-31

申请人： Ilia Moskovich ,  Aviram Amir ,  Itzhak Barak ,  Eliezer Ben Zeev

发明人： Ilia Moskovich ,  Aviram Amir ,  Itzhak Barak ,  Eliezer Ben Zeev

IPC分类号： G06F9/30 ,  G06F17/30

CPC分类号： G06F17/30336 ,  G06F9/30021 ,  G06F9/30036

摘要： An integrated circuit device comprises at least one digital signal processor, DSP, module, the at least one DSP module comprising a plurality of data registers and at least one data execution unit, DEU, module arranged to execute operations on data stored within the data registers. The at least one DEU module is arranged to, in response to receiving an extreme value index instruction, compare a previous extreme value located within a first data register set of the DSP module with at least one input vector data value located within a second data register set of the DSP module, and determine an extreme value thereof. The at least one DEU module is further arranged to, if the determined extreme value comprises an input vector data value located within the second data register set, store the determined extreme value in the first data register set, determine an index value for the determined extreme value, and store the determined index value in the first data register set.

摘要翻译： 集成电路装置包括至少一个数字信号处理器DSP模块，所述至少一个DSP模块包括多个数据寄存器和至少一个数据执行单元DEU模块，被配置为对存储在数据寄存器内的数据执行操作 。 所述至少一个DEU模块被布置成响应于接收到极值索引指令而将位于DSP模块的第一数据寄存器组内的先前极值与位于第二数据寄存器内的至少一个输入向量数据值进行比较 设置DSP模块，并确定其极值。 如果所确定的极值包括位于第二数据寄存器组内的输入矢量数据值，则至少一个DEU模块进一步被布置为将确定的极值存储在第一数据寄存器组中，确定所确定的极限值的指标值 值，并将确定的索引值存储在第一数据寄存器组中。

公开(公告)号：US20140019990A1

公开(公告)日：2014-01-16

申请号：US14006022

申请日：2011-03-30

申请人： Doron Schupper ,  Itzhak Barak ,  Uri Dayan ,  Noam Eshel-Goldman ,  Lev Vaskevich

发明人： Doron Schupper ,  Itzhak Barak ,  Uri Dayan ,  Noam Eshel-Goldman ,  Lev Vaskevich

IPC分类号： G06F9/46

CPC分类号： G06F9/461 ,  G06F9/3004 ,  G06F9/30076 ,  G06F9/30123 ,  G06F9/30145 ,  G06F9/30185 ,  G06F9/462

摘要： An integrated circuit device comprising an instruction processing module for performing operations on data in accordance with received instructions. The instruction processing module comprises a context selector unit arranged to selectively provide access to at least one process attribute(s) within a plurality of process contexts in accordance with at least one context selector value received thereby. The instruction processing module is arranged to receive an instruction comprising a context indication for a process attribute with which an operation is to be performed, provide the context selector value based at least partly on the context indication to the context selector unit, and execute the operation to be performed with the process attribute for at least one process context to which the context selector unit provides access in accordance with the context selector value.

摘要翻译： 一种集成电路装置，包括用于根据接收到的指令对数据执行操作的指令处理模块。 指令处理模块包括上下文选择器单元，其被布置为根据从其接收的至少一个上下文选择器值来选择性地提供对多个进程上下文中的至少一个进程属性的访问。 指令处理模块被配置为接收包括用于要执行操作的处理属性的上下文指示的指令，至少部分地基于上下文指示将上下文选择器值提供给上下文选择器单元，并且执行操作 用于根据上下文选择器值为上下文选择器单元提供访问的至少一个处理上下文的过程属性执行。

公开(公告)号：US07930522B2

公开(公告)日：2011-04-19

申请号：US12194279

申请日：2008-08-19

申请人： Guy Shumeli ,  Itzhak Barak ,  Uri Dayan ,  Amir Paran ,  Idan Rozenberg ,  Doron Schupper

发明人： Guy Shumeli ,  Itzhak Barak ,  Uri Dayan ,  Amir Paran ,  Idan Rozenberg ,  Doron Schupper

IPC分类号： G06F9/48

CPC分类号： G06F9/3842 ,  G06F9/30094

摘要： A method for speculative execution of instructions, the method includes: decoding a compare instruction; speculatively executing, in a continuous manner, conditional instructions that are conditioned by a condition that is related to a resolution of the compare instruction and are decoded during a speculation window that starts at the decoding of the compare instruction and ends when the compare instruction is resolved; and stalling an execution of a non-conditional instruction that is dependent upon an outcome of at least one of the conditional instructions, until the speculation window ends.

摘要翻译： 一种用于推测执行指令的方法，所述方法包括：对比较指令进行解码; 以连续的方式推测性地执行由与比较指令的分辨率相关的条件调节的条件指令，并且在比较指令的解码开始的推测窗口期间被解码并且当比较指令被解析时结束 ; 并且停止依赖于至少一个条件指令的结果的非条件指令的执行，直到投机窗口结束为止。

公开(公告)号：US09639362B2

公开(公告)日：2017-05-02

申请号：US14005475

申请日：2011-03-30

申请人： Noam Eshel-Goldman ,  Aviram Amir ,  Itzhak Barak ,  Amir Kleen

发明人： Noam Eshel-Goldman ,  Aviram Amir ,  Itzhak Barak ,  Amir Kleen

IPC分类号： G06F9/02 ,  G06F9/30

CPC分类号： G06F9/30185 ,  G06F9/30018

摘要： An integrated circuit device comprising at least one instruction processing module arranged to receive a bit-manipulation instruction, and in response to receiving the bit-manipulation instruction to select at least one bit from at least one source data register in accordance with a value of at least one control bit, select from candidate values a manipulation value for the at least one selected bit in accordance with a value of at least one further control bit, and store the selected manipulation value for the at least one selected bit in at least one output data register.

公开(公告)号：US20130297578A1

公开(公告)日：2013-11-07

申请号：US13978251

申请日：2011-01-31

申请人： Ilia Moskovich ,  Aviram Amir ,  Itzhak Barak ,  Eliezer Ben Zeev

发明人： Ilia Moskovich ,  Aviram Amir ,  Itzhak Barak ,  Eliezer Ben Zeev

IPC分类号： G06F17/30

CPC分类号： G06F17/30336 ,  G06F9/30021 ,  G06F9/30036

摘要： An integrated circuit device comprises at least one digital signal processor, DSP, module, the at least one DSP module comprising a plurality of data registers and at least one data execution unit, DEU, module arranged to execute operations on data stored within the data registers. The at least one DEU module is arranged to, in response to receiving an extreme value index instruction, compare a previous extreme value located within a first data register set of the DSP module with at least one input vector data value located within a second data register set of the DSP module, and determine an extreme value thereof. The at least one DEU module is further arranged to, if the determined extreme value comprises an input vector data value located within the second data register set, store the determined extreme value in the first data register set, determine an index value for the determined extreme value, and store the determined index value in the first data register set.

摘要翻译： 集成电路装置包括至少一个数字信号处理器DSP模块，所述至少一个DSP模块包括多个数据寄存器和至少一个数据执行单元DEU模块，被配置为对存储在数据寄存器内的数据执行操作 。 所述至少一个DEU模块被布置成响应于接收到极值索引指令而将位于DSP模块的第一数据寄存器组内的先前极值与位于第二数据寄存器内的至少一个输入向量数据值进行比较 设置DSP模块，并确定其极值。 如果所确定的极值包括位于第二数据寄存器组内的输入矢量数据值，则至少一个DEU模块进一步被布置为将确定的极值存储在第一数据寄存器组中，确定所确定的极限值的指标值 值，并将确定的索引值存储在第一数据寄存器组中。

公开(公告)号：US08266414B2

公开(公告)日：2012-09-11

申请号：US12194286

申请日：2008-08-19

申请人： Lev Vaskevich ,  Itzhak Barak ,  Amir Paran ,  Yuval Peled ,  Idan Rozenberg ,  Doron Schupper

发明人： Lev Vaskevich ,  Itzhak Barak ,  Amir Paran ,  Yuval Peled ,  Idan Rozenberg ,  Doron Schupper

IPC分类号： G06F9/40

CPC分类号： G06F9/325 ,  G06F9/381

摘要： A method for managing a hardware instruction loop, the method includes: (i) detecting, by a branch prediction unit, an instruction loop; wherein a size of the instruction loop exceeds a size of a storage space allocated in a fetch unit for storing fetched instructions; (ii) requesting from the fetch unit to fetch instructions of the instruction loop that follow the first instructions of the instruction loop; and (iii) selecting, during iterations of the instruction loop, whether to provide to a dispatch unit one of the first instructions of the instruction loop or another instruction that is fetched by the fetch unit; wherein the first instructions of the instruction loop are stored at the dispatch unit.

摘要翻译： 一种用于管理硬件指令循环的方法，所述方法包括：（i）由分支预测单元检测指令循环; 其中所述指令循环的大小超过在用于存储获取的指令的获取单元中分配的存储空间的大小; （ii）从提取单元请求获取遵循指令循环的第一指令的指令循环的指令; 以及（iii）在所述指令循环的迭代期间选择是否向所述调度单元提供所述指令循环的所述第一指令之一或由所述提取单元获取的另一指令; 其中指令循环的第一指令被存储在调度单元中。

公开(公告)号：US20100042811A1

公开(公告)日：2010-02-18

申请号：US12190291

申请日：2008-08-12

申请人： Yuval Peled ,  Itzhak Barak ,  Uri Dayan ,  Idan Rozenberg ,  Yoram Salant

发明人： Yuval Peled ,  Itzhak Barak ,  Uri Dayan ,  Idan Rozenberg ,  Yoram Salant

IPC分类号： G06F9/30

CPC分类号： G06F9/3885 ,  G06F9/30094 ,  G06F9/3804 ,  G06F9/3844

摘要： A method for managing branch instructions, the method includes: providing, to pipeline stages of a processor, multiple variable length groups of instructions; wherein each pipeline stage executes a group of instruction during a single execution cycle; receiving, at a certain execution cycle, multiple instruction fetch requests from multiple pipeline stages, each pipeline stage that generates an instruction fetch request stores a variable length group of instructions that comprises a branch instruction; sending to the fetch unit an instruction fetch command that is responsive to a first in order branch instruction in the pipeline stages; wherein if the first in order fetch command is a conditional fetch command then the instruction fetch command comprises a resolved target address; wherein the sending of the instruction fetch command is restricted to a single instruction fetch command per a single execution cycle.

摘要翻译： 一种用于管理分支指令的方法，所述方法包括：向处理器的流水线阶段提供多个可变长度的指令组; 其中每个流水线阶段在单个执行周期期间执行一组指令; 在某个执行周期接收来自多个流水线级的多个指令获取请求，生成指令提取请求的每个流水线级存储包括分支指令的可变长度的指令组; 向提取单元发送响应于流水线级中的第一顺序分支指令的指令获取命令; 其中如果所述第一顺序获取命令是条件获取命令，则所述指令获取命令包括解析的目标地址; 其中指令获取命令的发送被限制在单个执行周期中的单个指令获取命令。

公开(公告)号：US06928482B1

公开(公告)日：2005-08-09

申请号：US09606214

申请日：2000-06-29

申请人： Michael Ben Nun ,  Sagi Ravid ,  Itzhak Barak ,  Ofer Weill

发明人： Michael Ben Nun ,  Sagi Ravid ,  Itzhak Barak ,  Ofer Weill

IPC分类号： G06F15/16 ,  H04L29/06 ,  H04L29/08

CPC分类号： H04L67/1008 ,  H04L67/1002 ,  H04L67/1012 ,  H04L67/1019

摘要： An apparatus for distributing processing loads in a service aware network is provided. The apparatus contains a controller and a plurality of packet processors coupled to the controller. The controller receives a first data packet and determines whether or not any of the packet processors have been previously selected to process the first data packet based on a classification of the first data packet. When none of the packet processors has been previously designated to process the first data packet, the controller selects a first selected processor of the packet processors to process the first data packet. The first selected processor is selected based on processing load values respectively corresponding to processing loads of the packet processors. In addition, a method performed by the apparatus and a software program for controlling the controller are also provided.

摘要翻译： 提供一种用于在服务感知网络中分发处理负载的装置。 该装置包含耦合到控制器的控制器和多个分组处理器。 控制器接收第一数据分组，并且基于第一数据分组的分类来确定是否先前已经选择了任何分组处理器来处理第一数据分组。 当先前没有指定分组处理器来处理第一数据分组时，控制器选择分组处理器的第一选定处理器来处理第一数据分组。 第一选择的处理器是基于分别对应于分组处理器的处理负载的处理负载值来选择的。 此外，还提供了由该装置执行的方法和用于控制控制器的软件程序。

公开(公告)号：US20150082005A1

公开(公告)日：2015-03-19

申请号：US14396146

申请日：2012-05-29

申请人： Roy Glasner ,  Itzhak Barak ,  Yuval Feled ,  Idan Rozenberg ,  Lev Vaskevich

发明人： Roy Glasner ,  Itzhak Barak ,  Yuval Feled ,  Idan Rozenberg ,  Lev Vaskevich

IPC分类号： G06F9/30

CPC分类号： G06F9/30196 ,  G06F9/30145 ,  G06F9/30156 ,  G06F9/3853

摘要： A processing system comprises a processing device; a first instruction set encoded in a first encoding space and comprising one or more first instructions; a second instruction set encoded in a second encoding space different from the first encoding space and comprising two or more orthogonal second instructions; and an instruction encoder arranged to encode and encapsulate subsets of the second instructions in instruction containers, each instruction container sized to comprise a plurality of the second instructions.

摘要翻译： 处理系统包括处理装置; 编码在第一编码空间中并包括一个或多个第一指令的第一指令集; 编码在与第一编码空间不同的第二编码空间中并且包括两个或更多个正交的第二指令的第二指令集; 以及指令编码器，其被布置成编码并封装指令容器中的第二指令的子集，每个指令容器的尺寸被设计成包括多个第二指令。

公开(公告)号：US20140013088A1

公开(公告)日：2014-01-09

申请号：US14005475

申请日：2011-03-30

申请人： Noam Eshel-Goldman ,  Aviram Amir ,  Itzhak Barak ,  Amir Kleen

发明人： Noam Eshel-Goldman ,  Aviram Amir ,  Itzhak Barak ,  Amir Kleen

IPC分类号： G06F9/30

CPC分类号： G06F9/30185 ,  G06F9/30018

摘要： An integrated circuit device comprising at least one instruction processing module arranged to receive a bit-manipulation instruction, and in response to receiving the bit-manipulation instruction to select at least one bit from at least one source data register in accordance with a value of at least one control bit, select from candidate values a manipulation value for the at least one selected bit in accordance with a value of at least one further control bit, and store the selected manipulation value for the at least one selected bit in at least one output data register.

摘要翻译： 一种集成电路装置，包括至少一个指令处理模块，其被布置为接收位操作指令，并且响应于接收到所述位操作指令，以根据at的值从至少一个源数据寄存器中选择至少一个比特 至少一个控制位，根据至少一个另外的控制位的值，从候选值中选择所述至少一个所选位的操作值，并将所选择的所述操作值存储在至少一个输出中 数据寄存器。