公开(公告)号：US20100006838A1

公开(公告)日：2010-01-14

申请号：US12376045

申请日：2007-03-12

申请人： Masahiro Yoshida ,  Kazunori Tanimoto ,  Yasuhiro Mimura

发明人： Masahiro Yoshida ,  Kazunori Tanimoto ,  Yasuhiro Mimura

IPC分类号： H01L23/58 ,  G01R31/02

CPC分类号： G09G3/006 ,  G02F1/1345 ,  G02F1/13458 ,  G02F1/136286 ,  G02F2001/136254 ,  G02F2203/69 ,  G09G3/3225 ,  G09G3/3648 ,  G09G2300/0426 ,  H01L27/3276

摘要： By feeding inspection signals independent from each other to upper first and second gate lead inspection lines (52b, 52c), respectively, while maintaining the upper gate-side switching elements (40c) in an ON state, any short circuit between adjacent gate lines (40) of upper gate lines (40) and the like can be detected. By feeding inspection signals independent from each other to lower first and second gate lead inspection lines (53b, 53c), respectively, while maintaining lower gate-side switching elements (40c′) in an ON state, any short circuit between adjacent gate lines (40) of lower gate lines (40) and the like can be detected. By feeding inspection signals independent from each other to source lead inspection lines (55) while maintaining source-side switching elements (41) in an ON state, any short circuit between adjacent ones of source lines (41) and the like can be detected.

摘要翻译： 通过将检测信号彼此独立地馈送到上部第一和第二栅极引线检查线（52b，52c），同时保持上部栅极侧开关元件（40c）处于导通状态，相邻栅极线之间的任何短路 可以检测上部栅极线（40）等的40°。 通过彼此独立地馈送检查信号，分别降低第一和第二栅极引线检查线（53b，53c），同时保持下部栅极侧开关元件（40c'）处于导通状态，相邻栅极线之间的任何短路 可以检测下部栅极线（40）等的40°。 通过将检测信号彼此独立地馈送到源极检测线（55），同时将源极侧开关元件（41）保持在导通状态，可以检测相邻源极线（41）之间的任何短路等。

公开(公告)号：US08653827B2

公开(公告)日：2014-02-18

申请号：US12920857

申请日：2009-03-13

申请人： Kazunori Tanimoto ,  Isao Ogasawara ,  Masahiro Yoshida ,  Takehiko Kawamura ,  Hideaki Takizawa

发明人： Kazunori Tanimoto ,  Isao Ogasawara ,  Masahiro Yoshida ,  Takehiko Kawamura ,  Hideaki Takizawa

IPC分类号： G01R31/04

CPC分类号： G01R31/045 ,  G02F1/1345 ,  G02F1/136286 ,  G02F2001/13456 ,  G02F2001/136254

摘要： Provided is an active matrix substrate having improved display quality without forming an inspection line in a terminal arrangement region for inspecting short circuit between connection lines. Scanning lines (40) include first scanning lines having input ends for a scanning signal on one end side, and second scanning lines having input ends for a scanning signal the other end side. In a display region (4), the first scanning lines and the second scanning lines are formed alternately one by one. An active matrix substrate (2) includes a first inspection line (70) and a second inspection line (72) that cross each of a plurality of first connection lines (61), and a third inspection line (75) and a fourth inspection line (77) that cross each of a plurality of second connection lines (64). The first to the fourth inspection lines (70, 72, 75, 77) are formed in a frame-shaped wiring region (6), excluding the terminal arrangement region (5) and the display region (4).

摘要翻译： 提供一种具有改进的显示质量的有源矩阵基板，而不在端子排列区域中形成检查线，用于检查连接线之间的短路。 扫描线（40）包括在一端侧具有用于扫描信号的输入端的第一扫描线和具有用于扫描信号的另一端侧的输入端的第二扫描线。 在显示区域（4）中，第一扫描线和第二扫描线交替地一个一个地形成。 有源矩阵基板（2）包括跨越多个第一连接线（61）中的每一条的第一检查线（70）和第二检查线（72），以及第三检查线（75）和第四检查线 （77），其跨越多个第二连接线（64）中的每一个。 第一至第四检查线（70,72,75,77）形成在除端子排列区域（5）和显示区域（4）之外的框状布线区域（6）中。

公开(公告)号：US20110018142A1

公开(公告)日：2011-01-27

申请号：US12934896

申请日：2009-04-28

申请人： Takehiko Kawamura ,  Kazunori Tanimoto ,  Isao Ogasawara ,  Masahiro Yoshida ,  Hideaki Takizawa

发明人： Takehiko Kawamura ,  Kazunori Tanimoto ,  Isao Ogasawara ,  Masahiro Yoshida ,  Hideaki Takizawa

IPC分类号： H01L23/528 ,  G01R31/04

CPC分类号： G02F1/136286 ,  G02F1/1345 ,  G02F2001/13456 ,  G02F2001/136254 ,  G02F2001/13629 ,  H01L27/3276

摘要： An active matrix substrate is provided with first inspection wirings (70, 75) capable of inputting inspection signals to first switching wirings that are not adjacent to each other among the first switching wirings (69, 74) and to second switching wirings that are not adjacent to each other among the second switching wirings (69, 74), and second inspection wirings (72, 77) capable of inputting inspection signals to first switching wirings that are not adjacent to each other and not connected to the first inspection wirings among the first switching wirings (69, 74) and to second switching wirings that are not adjacent to each other and not connected to the first inspection wirings among the second switching wirings (69, 74).

摘要翻译： 有源矩阵基板设置有能够将检查信号输入到第一开关布线（69,74）中彼此不相邻的第一开关布线和不相邻的第二开关布线的第一检查布线（70,75） 以及第二检查布线（72,77），其能够将检查信号输入到彼此不相邻并且不连接到第一检查配线的第一切换布线的第一检测信号 开关布线（69,74）和与第二开关布线（69,74）之间不相邻并且不连接到第一检查布线的第二开关布线。

公开(公告)号：US07847577B2

公开(公告)日：2010-12-07

申请号：US12376045

申请日：2007-03-12

申请人： Masahiro Yoshida ,  Kazunori Tanimoto ,  Yasuhiro Mimura

发明人： Masahiro Yoshida ,  Kazunori Tanimoto ,  Yasuhiro Mimura

IPC分类号： G01R31/00

CPC分类号： G09G3/006 ,  G02F1/1345 ,  G02F1/13458 ,  G02F1/136286 ,  G02F2001/136254 ,  G02F2203/69 ,  G09G3/3225 ,  G09G3/3648 ,  G09G2300/0426 ,  H01L27/3276

摘要： By feeding inspection signals independent from each other to upper first and second gate lead inspection lines (52b, 52c), respectively, while maintaining the upper gate-side switching elements (40c) in an ON state, any short circuit between adjacent gate lines (40) of upper gate lines (40) and the like can be detected. By feeding inspection signals independent from each other to lower first and second gate lead inspection lines (53b, 53c), respectively, while maintaining lower gate-side switching elements (40c′) in an ON state, any short circuit between adjacent gate lines (40) of lower gate lines (40) and the like can be detected. By feeding inspection signals independent from each other to source lead inspection lines (55) while maintaining source-side switching elements (41) in an ON state, any short circuit between adjacent ones of source lines (41) and the like can be detected.

摘要翻译： 通过将检测信号彼此独立地馈送到上部第一和第二栅极引线检查线（52b，52c），同时保持上部栅极侧开关元件（40c）处于导通状态，相邻栅极线之间的任何短路 可以检测上部栅极线（40）等的40°。 通过彼此独立地馈送检查信号，分别降低第一和第二栅极引线检查线（53b，53c），同时保持下部栅极侧开关元件（40c'）处于导通状态，相邻栅极线之间的任何短路 可以检测下部栅极线（40）等的40°。 通过将检测信号彼此独立地馈送到源极检测线（55），同时将源极侧开关元件（41）保持在导通状态，可以检测相邻源极线（41）之间的任何短路等。

公开(公告)号：US20100245223A1

公开(公告)日：2010-09-30

申请号：US12744654

申请日：2008-09-08

申请人： Isao Asako ,  Junichi Morinaga ,  Sunao Aoki ,  Kazunori Tanimoto

发明人： Isao Asako ,  Junichi Morinaga ,  Sunao Aoki ,  Kazunori Tanimoto

IPC分类号： G09G3/36

CPC分类号： G02F1/136286 ,  G02F2001/13606

摘要： A plurality of source lines extending parallel to each other while alternately turning between a plurality of pixel electrodes provided in a delta arrangement, each have a plurality of first linear portions each extending along a side of the corresponding pixel electrode, a plurality of second linear portions each linked to the corresponding first linear portion and extending along a side of the corresponding pixel electrode to a middle portion of the side, and a plurality of protruding portions each extending from one end of the corresponding second linear portion along a side of the corresponding pixel electrode.

摘要翻译： 在以三角形排列设置的多个像素电极之间交替转动的多个源极线彼此平行延伸，每个具有沿对应的像素电极的一侧延伸的多个第一线性部分，多个第二线性部分 每个连接到相应的第一线性部分并且沿对应的像素电极的一侧延伸到侧面的中间部分，以及多个突出部分，每个突出部分沿相应的第二线性部分的一端沿对应的像素的一侧延伸 电极。

公开(公告)号：US20130335684A1

公开(公告)日：2013-12-19

申请号：US13981532

申请日：2012-01-18

申请人： Kazuhiro Yoshikawa ,  Kazunori Tanimoto ,  Masayuki Tsuji ,  Takayuki Hayano ,  Nobuhiro Nakata ,  Yoshihiro Asai ,  Masahiro Yoshida ,  Tatsuji Saitoh ,  Isao Ogasawara

发明人： Kazuhiro Yoshikawa ,  Kazunori Tanimoto ,  Masayuki Tsuji ,  Takayuki Hayano ,  Nobuhiro Nakata ,  Yoshihiro Asai ,  Masahiro Yoshida ,  Tatsuji Saitoh ,  Isao Ogasawara

IPC分类号： G02F1/1333

CPC分类号： G02F1/1333 ,  B32B37/12 ,  B32B2457/20 ,  G02F1/133351 ,  G02F1/13338 ,  G02F1/1347 ,  G02F2001/133368 ,  G02F2201/124 ,  G02F2201/503 ,  G02F2202/28 ,  G06F3/041 ,  G06F2203/04103

摘要： A functional panel (FP) includes a COM substrate (4) and an SEG substrate (3) that face each other. The functional panel (FP) is combined with a display panel (LP) via an adhesive. The COM substrate (4), which is provided farther from the display panel (LP) than the SEG substrate (3) is, has edges (E1, E2) that face each other. The SEG substrate (3), which is provided closer to the display panel (LP) than the COM substrate (4) is, has (i) an edge (E3) provided along and inside the edge (E1) when viewed from above and (ii) an edge (E4) provided along and inside the edge (E2) when viewed from above. This effectively prevents the occurrence of a defective external shape.

摘要翻译： 功能面板（FP）包括彼此相对的COM基板（4）和SEG基板（3）。 功能面板（FP）通过粘合剂与显示面板（LP）组合。 与显示面板（LP）比SEG基板（3）更远的COM基板（4）具有彼此相对的边缘（E1，E2）。 与COM基板（4）相比，靠近显示面板（LP）设置的SEG基板（3）具有（i）从上方观察边缘（E1）的边缘（E3），并且 （ii）当从上方观察时沿边缘（E2）设置的边缘（E4）。 这有效地防止了外部形状不良的发生。

公开(公告)号：US08582068B2

公开(公告)日：2013-11-12

申请号：US12934896

申请日：2009-04-28

申请人： Takehiko Kawamura ,  Kazunori Tanimoto ,  Isao Ogasawara ,  Masahiro Yoshida ,  Hideaki Takizawa

发明人： Takehiko Kawamura ,  Kazunori Tanimoto ,  Isao Ogasawara ,  Masahiro Yoshida ,  Hideaki Takizawa

IPC分类号： G02F1/1345 ,  G02F1/136 ,  G09G3/36 ,  H01L29/04

CPC分类号： G02F1/136286 ,  G02F1/1345 ,  G02F2001/13456 ,  G02F2001/136254 ,  G02F2001/13629 ,  H01L27/3276

摘要： An active matrix substrate is provided with first inspection wirings (70, 75) capable of inputting inspection signals to first switching wirings that are not adjacent to each other among the first switching wirings (69, 74) and to second switching wirings that are not adjacent to each other among the second switching wirings (69, 74), and second inspection wirings (72, 77) capable of inputting inspection signals to first switching wirings that are not adjacent to each other and not connected to the first inspection wirings among the first switching wirings (69, 74) and to second switching wirings that are not adjacent to each other and not connected to the first inspection wirings among the second switching wirings (69, 74).

摘要翻译： 有源矩阵基板设置有能够将检查信号输入到第一开关布线（69,74）中彼此不相邻的第一开关布线和不相邻的第二开关布线的第一检查布线（70,75） 以及第二检查布线（72,77），其能够将检查信号输入到彼此不相邻并且不连接到第一检查配线的第一切换布线的第一检测信号 开关布线（69,74）和与第二开关布线（69,74）之间不相邻并且不连接到第一检查布线的第二开关布线。

公开(公告)号：US07612834B2

公开(公告)日：2009-11-03

申请号：US11995146

申请日：2006-06-26

申请人： Kazunori Tanimoto ,  Tatsuji Saitoh

发明人： Kazunori Tanimoto ,  Tatsuji Saitoh

IPC分类号： G02F1/1335 ,  G02F1/1333

CPC分类号： G02B27/2214 ,  H04N13/31 ,  H04N2013/403 ,  H04N2213/001

摘要： A parallax barrier is manufactured by forming a light-blocking layer by patterning a metal layer or a resin layer on a barrier glass in a photolithography step. On a mask used in the photolithography step, some pitches between slits are different, the slits corresponding to portions whereupon the light-blocking layers are to be formed. In addition, on the mask, first pitches (for instance, 100) and second pitches (for instance 99.5), which can be actually formed with accuracy, are formed in a cycle, and the average of such pitches can be accord with a theoretical pitch distance (for instance, 99.99). Thus, in the parallax barrier to be used for a multiple display device, visibility of the entire screen can be improved, and the parallax barrier which can be manufactured by using the mask lithography technology having a limited accuracy, and a method for manufacturing such parallax barrier are provided.

摘要翻译： 通过在光刻步骤中在阻挡玻璃上图案化金属层或树脂层来形成遮光层来制造视差屏障。 在光刻步骤中使用的掩模上，狭缝之间的一些间距不同，对应于形成遮光层的部分的狭缝。 此外，在掩模上，以一个周期形成能够精确地实际形成的第一间距（例如100）和第二间距（例如99.5），这些间距的平均值可以符合理论 间距（例如99.99）。 因此，在用于多显示装置的视差屏障中，可以提高整个屏幕的可视性，并且可以通过使用具有有限精度的掩模光刻技术制造的视差屏障以及制造这种视差的方法 提供屏障。

公开(公告)号：US20090231255A1

公开(公告)日：2009-09-17

申请号：US12301132

申请日：2007-04-11

申请人： Kazunori Tanimoto ,  Junichi Morinaga

发明人： Kazunori Tanimoto ,  Junichi Morinaga

IPC分类号： G09G3/36

CPC分类号： G02F1/136286 ,  G02F2001/13456 ,  G02F2001/136254 ,  G09G3/006 ,  G09G3/20 ,  G09G2300/0413 ,  G09G2320/0219 ,  G09G2320/0233

摘要： A dummy line, which is disposed in a dummy pixel region (2) on the side of a test wiring region (1) and which has a parasitic capacitance effect like that of an adjacent scanning line (Gj) in an effective display region (3), is commonly used as a test switch line (1a). This test switch line (1a) is provided away from a dummy scanning line (DG) by intervals at which the scanning lines (Gj) are provided in the effective display region (3). As a result, it is possible to realize a display panel capable of reducing a frame area while keeping a test circuit region and the dummy pixel region in the frame area, and a display device having the display panel.

摘要翻译： 在虚拟像素区域（2）中，在有效显示区域（3）中具有与相邻的扫描线（Gj）相似的寄生电容效应的虚拟线， ），通常用作测试开关线（1a）。 该测试开关线（1a）通过设置在有效显示区域（3）中的扫描线（Gj）的间隔而远离虚拟扫描线（DG）提供。 结果，可以实现能够在保持测试电路区域和虚拟像素区域在帧区域中的同时缩小帧区域的显示面板和具有显示面板的显示装置。