公开(公告)号：US20060106974A1

公开(公告)日：2006-05-18

申请号：US10906167

申请日：2005-02-05

申请人： Ying-Chih Yang ,  Yuan-Ning Chen ,  Jen-Yi Liao

发明人： Ying-Chih Yang ,  Yuan-Ning Chen ,  Jen-Yi Liao

IPC分类号： G06F12/00

CPC分类号： G06F13/1694

摘要： A dynamic random access memory controller is suitable in controlling a first dynamic random access memory and a second dynamic random access memory, which two memory capacities are not the same. The judging circuit of the dynamic random access memory controller receives and judges whether or not a system addressing signal falls within a preset range, and outputs a judging signal. Furthermore, the transforming and shielding circuit transforms the system addressing signal and byte enable signal in accordance with the judging signal, and therefore obtains a memory addressing signal and a shielding signal for addressing the first and the second dynamic random access memories. Furthermore, the data interface circuit, in accordance with the judging signal, buffers or separates a system writing-in data signal, or, buffers or merges the memory data signal.

摘要翻译： 动态随机存取存储器控制器适用于控制第一动态随机存取存储器和第二动态随机存取存储器，其中两个存储器容量不相同。 动态随机存取存储器控制器的判断电路接收并判断系统寻址信号是否在预设范围内，并输出判断信号。 此外，变换和屏蔽电路根据判断信号变换系统寻址信号和字节使能信号，因此获得存储器寻址信号和用于寻址第一和第二动态随机存取存储器的屏蔽信号。 此外，数据接口电路根据判断信号缓冲或分离系统写入数据信号，或缓冲或合并存储器数据信号。

公开(公告)号：US20060083313A1

公开(公告)日：2006-04-20

申请号：US10907562

申请日：2005-04-06

申请人： Ying-Chih Yang ,  Han-Liang Chou ,  Jen-Yi Liao

发明人： Ying-Chih Yang ,  Han-Liang Chou ,  Jen-Yi Liao

IPC分类号： H04N11/02 ,  H04N7/12 ,  H04N11/04 ,  H04B1/66

CPC分类号： H04N19/433 ,  H04N19/102 ,  H04N19/159 ,  H04N19/172 ,  H04N19/176

摘要： A memory managing method for video data decoding process is provided. The memory managing method includes the following steps. A first frame having a first definition is stored, wherein the first frame is a first type or a second type. A second frame having the first definition is stored, wherein the second frame is the first type or the second type. A first frame having a second definition is stored in the memory space where the first frame having the first definition was originally stored, and the remaining memory space left after the original first frame having the first definition had been stored is released, wherein the memory space for storing the first frame having the first definition is greater than the memory space for storing the first frame having the second definition. A third frame having the second definition is stored, wherein the third frame is a third type.

摘要翻译： 提供了一种用于视频数据解码处理的存储器管理方法。 存储器管理方法包括以下步骤。 存储具有第一定义的第一帧，其中第一帧是第一类型或第二类型。 存储具有第一定义的第二帧，其中第二帧是第一类型或第二类型。 具有第二定义的第一帧被存储在具有最初存储第一定义的第一帧的存储器空间中，并且剩余的具有第一定义的原始第一帧之后剩余的剩余存储空间被释放，其中存储器空间 用于存储具有第一定义的第一帧大于用于存储具有第二定义的第一帧的存储器空间。 存储具有第二定义的第三帧，其中第三帧是第三类型。

公开(公告)号：US06704020B1

公开(公告)日：2004-03-09

申请号：US09704621

申请日：2000-11-03

申请人： Wen-Kuan Chen ,  Jen-Yi Liao

发明人： Wen-Kuan Chen ,  Jen-Yi Liao

IPC分类号： G09G318

CPC分类号： G11C7/16 ,  G11C7/1072 ,  G11C7/1075 ,  G11C2207/16 ,  H04N19/423 ,  H04N19/433 ,  H04N19/61

摘要： An architecture for video decompressor to efficiently access synchronously memory includes a synchronous memory device having an A-bank and B-bank for being stored with image data, and a memory controller for controlling data access to the synchronous memory to perform motion compensation and display. The image data has a plurality of scan lines and every four scan lines are grouped for being periodically arranged in the synchronous memory in such a manner that the A-bank is sequentially stored with (4N+0)-th and (4N+1)-th scan lines, and the B-bank is sequentially stored with the (4N+2)-th and (4N+3)-th scan lines, where N is a non-negative integer, so as to always perform memory operations by alternately accessing the A-bank and B-bank.

摘要翻译： 用于视频解压缩器以有效地访问同步存储器的架构包括具有用于存储图像数据的A组和B组的同步存储器件，以及用于控制对同步存储器的数据访问以执行运动补偿和显示的存储器控​​制器。 图像数据具有多条扫描线，并且每四条扫描线被分组，以便以（4N + 0）和（4N + 1）顺序地存储A-bank的方式周期性地排列在同步存储器中， 第（4N + 2）和第（4N + 3）扫描线依次存储B组，其中N是非负整数，以便总是执行存储器操作 交替访问A银行和B银行。