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37 条记录 (耗时 0.029 秒)

    Halogen-substituted quinoline derivatives and ectoparasite control agent
    13.
    发明授权
    Halogen-substituted quinoline derivatives and ectoparasite control agent 失效
    卤素取代喹啉衍生物和外寄生物控制剂

    公开(公告)号：US07022855B2

    公开(公告)日：2006-04-04

    申请号：US10681192

    申请日：2003-10-09

    申请人： Kazumi Yamamoto ,  Kazuhiko Oyama ,  Masayo Sakai ,  Ryo Horikoshi

    发明人： Kazumi Yamamoto ,  Kazuhiko Oyama ,  Masayo Sakai ,  Ryo Horikoshi

    IPC分类号： C07D221/06 ,  C07D219/04 ,  C07D215/16

    CPC分类号： C07D215/233

    摘要： An objective of the present invention is to provide an ectoparasite control agent for homothermic animals, which has high control effect and is safe. The compounds according to the present invention are compounds represented by formula (I) and salts thereof: wherein R1 represents optionally substituted alkyl; optionally substituted alkenyl; optionally substituted alkynyl; OR5 wherein R5 represents optionally substituted alkyl, optionally substituted alkenyl, or optionally substituted alkynyl; or SR5 wherein R5 is as defined above, R2 represents optionally substituted alkyl, any one of R3 and R4 represents hydrogen and the other represents fluorine, chlorine, bromine, or CF3, and X represents fluorine or chlorine.

    摘要翻译： 本发明的目的是提供一种具有高控制效果和安全性的嗜热动物的外寄生物控制剂。 根据本发明的化合物是由式（I）表示的化合物及其盐：其中R 1表示任选取代的烷基; 任选取代的烯基; 任选取代的炔基; 或其中R 5表示任选取代的烷基，任选取代的烯基或任选取代的炔基; 或其中R 5定义如上所述，R 2表示任选取代的烷基，R 3或O 2中的任何一个 >和R 4表示氢，另一个表示氟，氯，溴或CF 3，X表示氟或氯。

    Semiconductor device with delay locked loop
    14.
    发明授权
    Semiconductor device with delay locked loop 有权
    具有延迟锁定环路的半导体器件

    公开(公告)号：US06218877B1

    公开(公告)日：2001-04-17

    申请号：US09316037

    申请日：1999-05-21

    申请人： Kazuhiko Oyama ,  Hiroaki Kawano

    发明人： Kazuhiko Oyama ,  Hiroaki Kawano

    IPC分类号： H03L706

    CPC分类号： H03L7/0814 ,  G06F1/10

    摘要： A semiconductor device capable of easily adjusting an internal delay time is provided with a phase adjusting circuit, wherein the phase adjusting circuit comprises an internal delay reproduction circuit that reproduces the sum of a delay time required for an input signal to be input to the phase adjusting circuit and a delay time required for an output signal to be output from the phase adjusting circuit. A delay adjusting circuit connected with the internal delay reproduction circuit upstream or downstream relative thereto, generates a given delay time for adjusting the internal delay time reproduced by the internal delay reproduction circuit. A delay time control section is connected with the delay adjusting circuit and controls the delay time generated by the delay adjusting circuit. A phase comparator compares a phase of a signal passed through the delay time adjusting circuit with a signal inputted to the phase adjusting circuit. A delay selection circuit generates a given delay time for allowing a phase of the signal passed through the delay adjusting circuit to coincide with a phase of the signal inputted to the phase adjusting circuit, based on an output of the phase comparator.

    摘要翻译： 能够容易地调整内部延迟时间的半导体装置设置有相位调整电路，其中，相位调整电路包括内部延迟再现电路，其再现输入到相位调整的输入信号所需的延迟时间之和 电路和从相位调整电路输出输出信号所需的延迟时间。 与内部延迟再生电路连接的延迟调整电路相对于其上游或下游，产生用于调整由内部延迟再现电路再现的内部延迟时间的给定延迟时间。 延迟时间控制部分与延迟调节电路相连，并控制由延迟调节电路产生的延迟时间。 相位比较器将通过延迟时间调节电路的信号的相位与输入到相位调整电路的信号进行比较。 延迟选择电路基于相位比较器的输出，生成给定的延迟时间，以允许通过延迟调整电路的信号的相位与输入到相位调整电路的信号的相位一致。

    Communication apparatus and program provided with failure determining method and function
    18.
    发明授权
    Communication apparatus and program provided with failure determining method and function 有权
    通信设备和程序提供故障确定方法和功能

    公开(公告)号：US07549088B2

    公开(公告)日：2009-06-16

    申请号：US11151196

    申请日：2005-06-14

    申请人： Kazuhiko Oyama ,  Koji Hanada

    发明人： Kazuhiko Oyama ,  Koji Hanada

    IPC分类号： G06F11/00

    CPC分类号： G06F11/0727 ,  G06F11/0757 ,  G06F11/079 ,  H04L69/28 ,  H04L69/40

    摘要： Disclosed is a method of determining a failure in an information system including a transmission apparatus for transmitting control information and a reception apparatus connected to the transmission apparatus in such a manner as to enable information to be transmitted and received for receiving the control information, the reception apparatus transmitting response information to the received control information, wherein the transmission apparatus obtains, as first clock time, clock time of the most recently transmitted control information if the response information to the control information cannot be obtained within predetermined time period, wherein the transmission apparatus obtains, as second clock time, later one of clock time of the response information most recently transmitted by the reception apparatus and clock time of the control information most recently received by the reception apparatus, and wherein the transmission apparatus determines failure location based on the first clock time and the second clock time.

    摘要翻译： 公开了一种确定信息系统中的故障的方法，包括发送控制信息的发送装置和连接到发送装置的接收装置，使得能够发送和接收用于接收控制信息的信息，接收 设备向所接收的控制信息发送响应信息，其中，如果在预定时间段内不能获得对所述控制信息的响应信息，则所述发送设备获取最近发送的控制信息的时钟时间作为所述第一时钟时间，其中，所述发送设备 作为第二时钟时间，获得由接收装置最近发送的响应信息的时钟时间和由接收装置最近接收的控制信息的时钟时间之一，并且其中，传输装置基于fi确定故障位置 第一个时钟和第二个时钟时间。

    Operational amplifier and constant-current generation circuit using the same
    19.
    发明申请
    Operational amplifier and constant-current generation circuit using the same 审中-公开
    运算放大器和恒流发电电路使用相同

    公开(公告)号：US20070024367A1

    公开(公告)日：2007-02-01

    申请号：US11406328

    申请日：2006-04-19

    申请人： Kazuhiko Oyama

    发明人： Kazuhiko Oyama

    IPC分类号： H03F3/45

    CPC分类号： H03F3/45183 ,  H03F3/72 ,  H03F2203/45466 ,  H03F2203/45506 ,  H03F2203/45508 ,  H03F2203/45511 ,  H03F2203/45728

    摘要： Provided in a constant-current generation circuit is an OP AMP which includes a bias circuit, differential stage and amplification stage. In the OP AMP, a capacitance is provided between a control terminal which receives a start-up signal EN and a node NGATE. In a start-up operation of the circuit, the node NGATE can more rapidly rise from a VSS to a predetermined voltage by rising a specific voltage in synchronously with a switching timing of the start-up signal EN by virtue of a coupling effect.

    摘要翻译： 在恒流发生电路中提供的是包括偏置电路，差分级和放大级的OP AMP。 在OP AMP中，在接收启动信号EN的控制端和节点NGATE之间提供电容。 在电路的启动操作中，通过借助于耦合效应，通过与启动信号EN的切换定时同步地上升特定电压，节点NGATE可以更快地从VSS上升到预定电压。

    Amplifier and semiconductor storage device using the same
    20.
    发明授权
    Amplifier and semiconductor storage device using the same 失效
    放大器和半导体存储器件使用相同

    公开(公告)号：US06956781B2

    公开(公告)日：2005-10-18

    申请号：US10768061

    申请日：2004-02-02

    申请人： Kazuhiko Oyama

    发明人： Kazuhiko Oyama

    IPC分类号： G11C16/06 ,  G11C7/02 ,  G11C7/06 ,  G11C16/28 ,  H03F3/45

    CPC分类号： G11C7/062 ,  G11C16/28

    摘要： When a first memory cell storing data ‘0’ is read, an associated word line is set at an ‘H’ level, and an associated NMOS is turn on by a signal having an ‘H’ level so as to select the first memory cell. In the first memory cell, a drain voltage is reduced to a grounding level via the NMOS, and an electrical potential difference is generated between a source and the drain. However, no channel is formed so that no electrical current flows. Since a parasitic capacitance exists between associated bit lines, the electrical potential of a node is reduced to the ground level due to the coupling effect of the parasitic capacitance. Accordingly, a charging current flows to the node. In addition, a direct current flows from the node to the ground via another NMOS. Consequently, electrical charging to the parasitic capacitance starts earlier, and a reading delay time can be reduced.

    摘要翻译： 当读出存储数据“0”的第一存储单元时，相关联的字线被设置为“H”电平，并且相关联的NMOS由具有“H”电平的信号导通，以便选择第一存储单元 。 在第一存储单元中，通过NMOS将漏极电压降低到接地电平，并且在源极和漏极之间产生电位差。 然而，没有形成通道，使得没有电流流动。 由于在相关联的位线之间存在寄生电容，所以由于寄生电容的耦合效应，节点的电位降低到接地电平。 因此，充电电流流向节点。 此外，直流电经由另一个NMOS从节点流向地。 因此，对寄生电容的充电开始较早，并且可以减少读取延迟时间。