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11.发明授权公开(公告)号：US11017141B2
公开(公告)日：2021-05-25
申请号：US16874224
申请日：2020-05-14
Inventor： Heiko Kalte , Dominik Lubeley , Marc Schlenger
IPC: G06F30/38 , G06F30/34 , G06F115/02 , G06F117/02
Abstract: A method for troubleshooting the program logic of a computer system. A first logic circuit and a first monitoring circuit, which is communicatively isolated from it, are programmed on a first programmable gate array of the computer system. A second logic circuit and a second monitoring circuit, which is communicatively isolated from it, are programmed on a second programmable gate array of the computer system. After an error has been detected in the program logic of the computer system, a first signal line, which applies a signal from the first logic circuit to a first signal input of the first monitoring circuit, is programmed in the first programmable gate array without changing the first logic circuit, and a second signal line, which applies a signal from the second logic circuit, is programmed in the second programmable gate array without changing the second logic circuit.
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Patent Agency Ranking
公开(公告)号：US10394989B2
公开(公告)日：2019-08-27
申请号：US15585335
申请日：2017-05-03
Inventor： Heiko Kalte , Dominik Lubeley
IPC: G06F17/50
Abstract: A method for creating an FPGA netlist generated from an FPGA source code and at least one shadow register. The FPGA source code defines at least one function and at least one signal. The shadow register is assigned to the at least one signal, and is arranged and provided to store the value of the assigned signal at runtime. An option for reading out the stored signal value at runtime is provided. The function defined in the FPGA source code is not changed by the shadow register. The function described by the FPGA source code is executed by the FPGA, and a functional decoupling of the shadow register from the function described in the FPGA source code is provided. Via the decoupling, the shadow register maintains the signal value stored at the time of the decoupling while the function described in the FPGA source code is being executed.
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公开(公告)号：US20180323784A1
公开(公告)日：2018-11-08
申请号：US15964245
申请日：2018-04-27
Inventor： Dominik Lubeley , Marc Schlenger , Heiko Kalte
IPC: H03K19/003 , H03K19/0175 , G01R31/317
CPC classification number: H03K19/003 , G01R31/317 , G01R31/31717 , G06F13/4072 , H03K19/017509 , H03K19/017581
Abstract: A method for detecting the topology of electrical wiring between at least two field-programmable gate arrays (FPGAs) includes implementing a first receive register on a second interface pin; implementing a first send register on a first driver; activating the first driver via a first activation signal; emitting, by the first driver, a first signal, wherein the first signal is defined by the first send register; reading out, by a first receive register, whether the first signal is received at the second interface pin; and allocating the second interface pin to the first interface pin if the first signal from the first driver is received at the second interface pin.
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公开(公告)号：US10102325B2
公开(公告)日：2018-10-16
申请号：US15291113
申请日：2016-10-12
Inventor： Dominik Lubeley , Marc Schlenger , Heiko Kalte
Abstract: A method for determining the power consumption of a programmable logic device, in which at least one configuration parameter is determined in accordance with a predefined configuration and at least one device parameter is determined in accordance with the programmable logic device. The predefined configuration is designed such that the programmable logic device exchanges data with a computing unit through at least one interface pin and receives data from at least one signal source and/or sends it to at least one signal receiver through at least one interface pin. At least one data characteristic of the data exchanged between the computing unit and the programmable logic device as well as at least one signal characteristic of the data received from the at least one signal source and/or sent to the at least one signal receiver are determined.
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公开(公告)号：US09870440B2
公开(公告)日：2018-01-16
申请号：US14711116
申请日：2015-05-13
Inventor： Heiko Kalte , Dominik Lubeley
IPC: G06F17/50
CPC classification number: G06F17/5054
Abstract: A method for generating a netlist of an FPGA program. The model of the FPGA program is composed of at least two components, each component being assigned a separate partition on the FPGA. An independent build is carried out for each component and an overall classification is generated from the components, wherein the build jobs are automatically started after a trigger event and the trigger event is a saving of a component, the exiting of a component of the design, or a time-controlled, automated initiation of a build.
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16.发明申请公开(公告)号：US20170329732A1
公开(公告)日：2017-11-16
申请号：US15586798
申请日：2017-05-04
Inventor： Heiko Kalte , Dominik Lubeley
IPC: G06F13/362 , G06F13/40
CPC classification number: G06F13/3625 , G06F13/00 , G06F13/4068 , G06F17/5031 , G06F2217/84 , H04L7/0041
Abstract: Method for temporally synchronizing the output of signals and/or temporally synchronizing the processing of captured signals on a plurality of input and/or output channels of an electronic circuit, comprising the following steps: (a) combining a number of channels, in particular a proportion of all channels of the circuit, to form a logical group; (b) retrieving the channel latency of each channel belonging to the group from a data source; (c) determining the greatest channel latency from all retrieved channel latencies and at least temporarily storing the greatest channel latency as the group latency; (d) for each channel belonging to the group: determining the temporal difference between the group latency and the retrieved channel latency of the respective channel and storing the determined difference as a channel-associated latency offset in a memory, in particular a memory of the circuit; and (e) influencing the signal propagation via a respective channel on the basis of at least its respective stored latency offset.
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