公开(公告)号：US12093618B2

公开(公告)日：2024-09-17

申请号：US18314007

申请日：2023-05-08

Applicant: Celera, Inc.

Inventor： Calum MacRae ,  John Mason ,  Karen Mason

IPC: G06F30/327 ,  G06F30/31 ,  G06F30/347 ,  G06F30/367 ,  G06F30/373 ,  G06F30/38 ,  G06F30/392 ,  G06F30/398 ,  G06F111/12

CPC classification number: G06F30/327 ,  G06F30/31 ,  G06F30/347 ,  G06F30/367 ,  G06F30/38 ,  G06F30/392 ,  G06F30/398 ,  G06F30/373 ,  G06F2111/12

Abstract: In some embodiments, a computer-implemented method of generating a resistor comprises receiving a first resistor value, converting the resistor value into a plurality of resistor layout segments, and automatically placing the plurality of resistor layout segments based on one or more layout placement instructions to form the first resistor value.

公开(公告)号：US12079555B2

公开(公告)日：2024-09-03

申请号：US18314004

申请日：2023-05-08

Applicant: Celera, Inc.

Inventor： Calum MacRae ,  Jim LoCascio ,  Karen Mason ,  John Mason ,  Richard Philpott ,  Muhammed Abid Hussain

IPC: G06F30/327 ,  G06F30/31 ,  G06F30/347 ,  G06F30/367 ,  G06F30/373 ,  G06F30/38 ,  G06F30/392 ,  G06F30/398 ,  G06F111/12

CPC classification number: G06F30/327 ,  G06F30/31 ,  G06F30/347 ,  G06F30/367 ,  G06F30/38 ,  G06F30/392 ,  G06F30/398 ,  G06F30/373 ,  G06F2111/12

Abstract: Automated circuit generation is disclosed. In some embodiments, parameters are received and a circuit schematic is generated automatically by software. In some embodiment, parameters are received and a circuit layout is generated automatically by software. In some embodiments, a design interface may be used to create a behavioral model of a circuit. Software may generate a circuit specification to generate a schematic. In various embodiments, circuit component values may be determined and generated. Certain embodiments pertain to automating layout of circuits. Software may receive parameters for functional circuit components and generate a circuit schematic and/or a layout. The present techniques are particularly useful for automatically generating analog circuits.

公开(公告)号：US20240249055A1

公开(公告)日：2024-07-25

申请号：US18439639

申请日：2024-02-12

Applicant: ANSYS, INC.

Inventor： Joao Geada ,  Nicholas Lee Rethman

IPC: G06F30/367 ,  G06F30/3312 ,  G06F30/3315 ,  G06F30/38 ,  G06F119/12

CPC classification number: G06F30/367 ,  G06F30/3312 ,  G06F30/3315 ,  G06F30/38 ,  G06F2119/12

Abstract: Methods and systems for performing timing analysis during the design of a circuit are described. In one embodiment, a simulation system can generate an effective resistance value (or an impedance value based on the effective resistance value) for an instance and use the effective resistance value in a simulation to determine a minimum timing delay for the instance when only the instance switches during such simulations.

公开(公告)号：US12008296B2

公开(公告)日：2024-06-11

申请号：US18314000

申请日：2023-05-08

Applicant: Celera, Inc.

Inventor： Calum MacRae ,  John Mason ,  Karen Mason

IPC: G06F30/327 ,  G06F30/31 ,  G06F30/347 ,  G06F30/367 ,  G06F30/373 ,  G06F30/38 ,  G06F30/392 ,  G06F30/398 ,  G06F111/12

CPC classification number: G06F30/327 ,  G06F30/31 ,  G06F30/347 ,  G06F30/367 ,  G06F30/38 ,  G06F30/392 ,  G06F30/398 ,  G06F30/373 ,  G06F2111/12

Abstract: Automated circuit generation is disclosed. In some embodiments, parameters are received and a circuit schematic is generated automatically by software. In some embodiment, parameters are received and a circuit layout is generated automatically by software. In some embodiments, a design interface may be used to create a behavioral model of a circuit. Software may generate a circuit specification to generate a schematic. In various embodiments, circuit component values may be determined and generated. Certain embodiments pertain to automating layout of circuits. Software may receive parameters for functional circuit components and generate a circuit schematic and/or a layout. The present techniques are particularly useful for automatically generating analog circuits.

公开(公告)号：US11934760B1

公开(公告)日：2024-03-19

申请号：US17645882

申请日：2021-12-23

Applicant: ANSYS, INC.

Inventor： Joao Geada ,  Nicholas Lee Rethman

IPC: G06F30/30 ,  G06F30/3312 ,  G06F30/3315 ,  G06F30/367 ,  G06F30/38 ,  G06F119/12

CPC classification number: G06F30/367 ,  G06F30/3312 ,  G06F30/3315 ,  G06F30/38 ,  G06F2119/12

Abstract: Methods and systems for performing timing analysis during the design of a circuit are described. In one embodiment, a simulation system can generate an effective resistance value (or an impedance value based on the effective resistance value) for an instance and use the effective resistance value in a simulation to determine a minimum timing delay for the instance when only the instance switches during such simulations.

公开(公告)号：US11907719B2

公开(公告)日：2024-02-20

申请号：US16914009

申请日：2020-06-26

Applicant: Intel Corporation

Inventor： Martin Langhammer ,  Dongdong Chen ,  Jason R. Bergendahl

IPC: G06F9/30 ,  G06N20/00 ,  G06F30/343 ,  G06F30/34 ,  G06F30/38 ,  G06F7/50 ,  G06F7/523 ,  H03K19/17748 ,  H03M7/24 ,  G06F7/556 ,  H03K19/177 ,  G06F7/483

CPC classification number: G06F9/30101 ,  G06F7/50 ,  G06F7/523 ,  G06F7/556 ,  G06F9/30105 ,  G06F30/34 ,  G06F30/343 ,  G06F30/38 ,  G06N20/00 ,  H03K19/177 ,  H03K19/17748 ,  H03M7/24 ,  G06F7/483

Abstract: The present disclosure describes a digital signal processing (DSP) block that includes a plurality of columns of weight registers and a plurality of inputs configured to receive a first plurality of values and a second plurality of values. The first plurality of values is stored in the plurality of columns of weight registers after being received. Additionally, the DSP block includes a plurality of multipliers configured to simultaneously multiply each value of the first plurality of values by each value of the second plurality of values.

公开(公告)号：US11544435B1

公开(公告)日：2023-01-03

申请号：US17353208

申请日：2021-06-21

Applicant: Synopsys, Inc.

Inventor： Dmitry Korchemny ,  Ilya Kudryavtsev ,  Eduard Cerny ,  Dmitriy Mosheyev

IPC: G06F30/3308 ,  G06F30/38 ,  G06F30/327 ,  G06F30/367 ,  G06F30/398

Abstract: The present disclosure generally relates to an analog mixed-signal (AMS) design verification system. In particular, the present disclosure relates to a system and method for system verification. One example method includes: obtaining an electronic representation of the circuit design; generating at least a portion of a waveform using the electronic representation of the circuit to obtain a first segment of the waveform associated with the circuit; converting, via the one or more processors, one or more measurement functions to code for performing the one or more computations on the first segment of the waveform; performing one or more computations on the first segment of the waveform using the code; and identifying when a behavior of the circuit violates a design specification based on whether a result of the one or more computations meets a threshold.

公开(公告)号：US12093619B2

公开(公告)日：2024-09-17

申请号：US18314029

申请日：2023-05-08

Applicant: Celera, Inc.

Inventor： Calum MacRae ,  John Mason ,  Karen Mason

IPC: G06F30/327 ,  G06F30/31 ,  G06F30/347 ,  G06F30/367 ,  G06F30/373 ,  G06F30/38 ,  G06F30/392 ,  G06F30/398 ,  G06F111/12

CPC classification number: G06F30/327 ,  G06F30/31 ,  G06F30/347 ,  G06F30/367 ,  G06F30/38 ,  G06F30/392 ,  G06F30/398 ,  G06F30/373 ,  G06F2111/12

Abstract: In some embodiments, information specifying a transistor to be generated is received, the information comprising an on resistance. A total width of a gate of the transistor to be generated is determined based at least on the on resistance. A first width, a number of fingers (F), and a number of device cells (P) are determined based on the total width. A transistor level schematic is generated comprising one or more transistors configured with the first width and the number of fingers (F). A layout is generated, wherein the layout comprises P device cells, each device cell comprising a plurality of gates corresponding to said number of fingers (F) each gate having said first width, wherein the device cells are configured in a two-dimensional array.

公开(公告)号：US11815971B2

公开(公告)日：2023-11-14

申请号：US17156910

申请日：2021-01-25

Applicant: Texas Instruments Incorporated

Inventor： Lakshmanan Balasubramanian ,  Aswani Kumar Golla ,  Venkatraman Ramakrishnan ,  Sushmitha Tudiyadka Girijashankar

IPC: G06F30/30 ,  G06F1/26 ,  G06F30/38 ,  H03K3/037

CPC classification number: G06F1/266 ,  G06F30/38 ,  H03K3/037

Abstract: A method for boundary port modelling that correctly handles back-to-back isolation intent, level shifter intent and voltage level association, by providing hard association of power domains to soft data objects, such as wires. The method includes identifying a boundary port in a detailed power intent (DPI) for a soft design object (SDO). A non-wire object is inserted in the SDO for the boundary port. In the DPI, a power domain of the boundary port is assigned to the non-wire object.

公开(公告)号：US20230274059A1

公开(公告)日：2023-08-31

申请号：US18314029

申请日：2023-05-08

Applicant: Celera, Inc.

Inventor： Calum MacRae ,  John Mason ,  Karen Mason

IPC: G06F30/327 ,  G06F30/392 ,  G06F30/398 ,  G06F30/367 ,  G06F30/38 ,  G06F30/31

CPC classification number: G06F30/327 ,  G06F30/392 ,  G06F30/398 ,  G06F30/367 ,  G06F30/38 ,  G06F30/31 ,  G06F2111/12

Abstract: Automated circuit generation is disclosed. In some embodiments, parameters are received and a circuit schematic is generated automatically by software. In some embodiment, parameters are received and a circuit layout is generated automatically by software. In some embodiments, a design interface may be used to create a behavioral model of a circuit. Software may generate a circuit specification to generate a schematic. In various embodiments, circuit component values may be determined and generated. Certain embodiments pertain to automating layout of circuits. Software may receive parameters for functional circuit components and generate a circuit schematic and/or a layout. The present techniques are particularly useful for automatically generating analog circuits.