公开(公告)号：US11625172B2

公开(公告)日：2023-04-11

申请号：US17349306

申请日：2021-06-16

Applicant: SanDisk Technologies LLC

Inventor： Xiang Yang ,  Toru Miwa ,  Ken Oowada ,  Gerrit Jan Hemink

IPC: G06F3/06

Abstract: Apparatuses and techniques are described for programming data in memory cells while concurrently storing backup data. One or more initial pages of data are programmed into both a primary block and a first backup block in a first program pass. A power loss then occurs which can corrupt the data or otherwise prevent reading of the one or more initial pages of data from the primary block. The one or more initial pages of data are read from the first backup block and used to perform a second program pass in which one or more additional pages of data are programmed into the primary block. Single bit per cell data can be stored in a second backup block to decode the one or more initial pages of data as read from the first backup block.

公开(公告)号：US20230076245A1

公开(公告)日：2023-03-09

申请号：US17469016

申请日：2021-09-08

Applicant: SanDisk Technologies LLC

Inventor： Xiang Yang ,  Deepanshu Dutta ,  Gerrit Jan Hemink

IPC: G11C16/08 ,  G11C16/04 ,  G11C16/10 ,  G11C16/26

Abstract: An apparatus includes a control circuit configured to connect to first word lines of a first vertical sub-block and second word lines of a second vertical sub-block. The first vertical sub-block and the second vertical sub-block include memory cells connected in series in NAND strings, each NAND string including memory cells coupled to the first word lines in series with memory cells connected to the second word lines. The control circuit is configured to program or sense memory cells along a selected first word line of the first vertical sub-block while applying a first voltage to second word lines that are connected to programmed memory cells and applying a second voltage to second word lines that are connected to unprogrammed memory cells.

公开(公告)号：US20230012977A1

公开(公告)日：2023-01-19

申请号：US17368727

申请日：2021-07-06

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Xiang Yang

IPC: G11C11/56 ,  G11C16/04 ,  G11C16/08 ,  G11C16/10 ,  G11C16/26

Abstract: In a three dimensional non-volatile memory structure that etches part of the top of the memory structure (including a portion of the select gates), data is stored on a majority (or all but one) of the word lines as x bits per memory cell while data is stored on a top edge word line that is closest to the etching with variable bits per memory cell. In one example embodiment that implements vertical NAND strings, memory cells connected to the top edge word line and that are on NAND strings adjacent the etching store data as n bits per memory cell and memory cells connected to the top edge word line and that are on NAND strings not adjacent the etching store data as m bits per memory cell, where m>x>n.

公开(公告)号：US11551781B1

公开(公告)日：2023-01-10

申请号：US17349321

申请日：2021-06-16

Applicant: SanDisk Technologies LLC

Inventor： Xiang Yang ,  Toru Miwa ,  Ken Oowada ,  Gerrit Jan Hemink

IPC: G11C16/26 ,  G11C29/00 ,  G11C29/02 ,  G11C16/34 ,  G11C16/10

Abstract: Apparatuses and techniques are described for programming data in memory cells while concurrently storing backup data. Initial pages of multiple bit per cell data are encoded to obtain at least first and second pages of single bit per cell data. The initial pages of multiple bit per cell data are programmed into a primary set of memory cells, while concurrently the first and second pages of single bit per cell data are programmed into first and second backup sets of memory cells, respectively. In the event of a power loss, the first and second pages of single bit per cell data are read from the first and second backup sets of memory cells, and decoded to recover the initial pages of multiple bit per cell data.

公开(公告)号：US11551765B2

公开(公告)日：2023-01-10

申请号：US17329617

申请日：2021-05-25

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Xiang Yang ,  Dengtao Zhao

IPC: G11C11/34 ,  G11C16/16 ,  G11C16/26 ,  G11C16/24 ,  G11C16/32 ,  G11C16/30

Abstract: A non-volatile memory system adjusts the speed of a memory operation for a subset of non-volatile memory cells. For example, during a GIDL based erase process, the GIDL generation can be dampened for a subset of memory cells (e.g., for a set of NAND strings, or one or more sub-blocks).

公开(公告)号：US20220399065A1

公开(公告)日：2022-12-15

申请号：US17344135

申请日：2021-06-10

Applicant: SanDisk Technologies LLC

Inventor： Xiang Yang

IPC: G11C16/34 ,  G11C16/16 ,  G11C16/26

Abstract: A method for dynamically adjusting an erase voltage level to be applied in a subsequent erase cycle, comprising: in a current erase cycle, initiating a current erase/verify loop by applying an initial stored erase voltage level according to an erase sequence in which each successive erase/verify loop is incremented by a pre-determined voltage amount, storing an erase/verify loop count, and determining whether the current erase cycle is complete according to a pass criterion. If the erase cycle is complete, a determination is made as to whether the stored erase/verify loop count equals a pre-defined threshold count. Further, if the stored count does not equal the pre-defined threshold count, the initial stored erase voltage level is adjusted such that, upon applying the adjusted erase voltage level in a subsequent erase cycle, an erase/verify loop count will now equal the pre-defined threshold count.

公开(公告)号：US20220399064A1

公开(公告)日：2022-12-15

申请号：US17343486

申请日：2021-06-09

Applicant: SanDisk Technologies LLC

Inventor： Xiang Yang

IPC: G11C16/34 ,  G11C16/04

Abstract: This disclosure proposes a method to save P/E cycling information inside NAND by using 2-byte column in programmable selective devices (e.g., SGD). The proposed method is a one-way programming method, and does not perform an erase operation within the 2-byte column. The proposed methods described herein can reduce the burden of relying upon controller SRAM/DRAM. Additionally, by storing the P/E cycling information in NAND, the P/E cycling is not lost due to a power loss event. At least one application advantageous for using NAND to store P/E cycling information includes wear leveling.

公开(公告)号：US11456042B1

公开(公告)日：2022-09-27

申请号：US17229705

申请日：2021-04-13

Applicant: SanDisk Technologies LLC

Inventor： Xiang Yang ,  Jiahui Yuan ,  Abhijith Prakash

IPC: G11C11/34 ,  G11C16/34 ,  G11C16/10 ,  G11C16/30 ,  G11C16/26 ,  G11C16/08

Abstract: Apparatuses and techniques are described for reducing damage to memory cells during single bit per cell programming. An initial program pulse in a single bit per cell program operation has a lower, first program level followed by a higher, second program level. As a result of the lower, first program level, the electric field across the memory cells is reduced. The step up time from the first program level to the second program level can be reduced by concurrently stepping up pass voltages of the adjacent unselected word lines. If an additional program pulse is applied, the step up in the program pulse can be omitted. The magnitude of the first program level can be adjusted based on factors such as temperature, number of program-erase cycles, selected sub-block position and selected word line position.

公开(公告)号：US10984876B2

公开(公告)日：2021-04-20

申请号：US16445367

申请日：2019-06-19

Applicant: SanDisk Technologies LLC

Inventor： Piyush Dak ,  Mohan Dunga ,  Chao Qin ,  Muhammad Masuduzzaman ,  Xiang Yang

IPC: G11C16/34 ,  G11C16/32 ,  G11C16/26 ,  G11C16/10

Abstract: Various methods include receiving, by a controller, a temperature reading of a memory array, the temperature reading includes a temperature value; determining the temperature value is below a first threshold; in response, modifying a duration of a verify cycle of a write operation to create a modified verify cycle; then programming a first data into the memory array using the write operation that uses the modified verify cycle. Methods additionally include receiving a second temperature reading of the memory array, the second temperature reading includes a second temperature value; determining the second temperature value is below a second threshold, in response, decreasing the duration of a verify cycle of a verify cycle to create a second verify cycle, where the second verify cycle is shorter than the modified verify cycle; and then programming a second data into the memory array using the write operation that uses the second verify cycle.

公开(公告)号：US20210027850A1

公开(公告)日：2021-01-28

申请号：US17066663

申请日：2020-10-09

Applicant: SanDisk Technologies LLC

Inventor： Xiang Yang ,  Yu-Chung Lien

IPC: G11C16/34 ,  G11C16/24 ,  G11C16/08 ,  G11C16/04 ,  G11C16/26

Abstract: A methodology and structure for performing an erase verify in non-volatile memory is described. Both the odd wordlines and the even wordlines are driven to a high voltage level. This can be done simultaneously. The simultaneous charging of both the odd wordlines and the even wordlines, even when the erase verify will occur on only one of the odd or even wordlines reduces RC delay in the charging of the wordlines. After the odd and even wordlines are charged, then one set of wordlines, either the odd or even wordlines, is dropped to the erase verify voltage. The erase sense operation is then performed.