公开(公告)号：US09984191B2

公开(公告)日：2018-05-29

申请号：US14473614

申请日：2014-08-29

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Tung-Heng Hsieh ,  Sheng-Hsiung Wang ,  Hui-Zhong Zhuang ,  Yu-Cheng Yeh ,  Tsung-Chieh Tsai ,  Juing-Yi Wu ,  Liang-Yao Lee ,  Jyh-Kang Ting

IPC: G06F17/50 ,  H01L27/02 ,  H01L27/118

CPC classification number: G06F17/5072 ,  G06F17/5077 ,  G06F17/5081 ,  H01L27/0207 ,  H01L27/11807 ,  H01L2027/11874

Abstract: A post placement abutment treatment for cell row design is provided. In an embodiment a first cell and a second cell are placed in a first cell row and a third cell and a fourth cell are placed into a second cell row. After placement vias connecting power and ground rails to the underlying structures are analyzed to determine if any can be merged or else removed completely. By merging and removing the closely placed vias, the physical limitations of photolithography may be by-passed, allowing for smaller structures to be formed.

公开(公告)号：US09691666B2

公开(公告)日：2017-06-27

申请号：US15149925

申请日：2016-05-09

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Lee-Chung Lu ,  Hui-Zhong Zhuang ,  Li-Chun Tien

IPC: H01L21/82 ,  H01L21/8234 ,  H01L29/417 ,  H01L27/02 ,  H01L21/768 ,  H01L29/423 ,  H01L21/3205 ,  H01L29/06 ,  H01L27/32

CPC classification number: H01L21/823475 ,  H01L21/32055 ,  H01L21/76802 ,  H01L21/76895 ,  H01L21/823418 ,  H01L27/0207 ,  H01L27/326 ,  H01L29/0649 ,  H01L29/41725 ,  H01L29/41775 ,  H01L29/4238

Abstract: An integrated circuit is provided. The integrated circuit includes a first contact disposed over a first source/drain region, a second contact disposed over a second source/drain region, a polysilicon disposed over a gate, the polysilicon interposed between the first contact and the second contact, a first polysilicon contact bridging the polysilicon and the first contact within an active region, and an output structure electrically coupled to the first polysilicon contact.

公开(公告)号：US09626472B2

公开(公告)日：2017-04-18

申请号：US14555175

申请日：2014-11-26

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Ting-Wei Chiang ,  Li-Chun Tien ,  Hui-Zhong Zhuang ,  Zhe-Wei Jiang

IPC: G06F17/50 ,  H01L27/088

CPC classification number: G06F17/5072 ,  H01L27/0886

Abstract: A method of forming a layout design is disclosed. The method includes placing a first set of layout patterns in a first layout layer and placing a second set of layout patterns in a second layout layer. The first set of layout patterns is aligned with one or more grid lines of a first set of grid lines. The first set of grid lines extends along a first direction, where two grid lines of the first set of grid lines overlap two cell boundaries of a standard cell layout. The second set of layout patterns is aligned with one or more grid lines of a second set of grid lines. The second set of grid lines extends along the first direction and has at least two different line pitches, where two grid lines of the second set of grid lines overlap two cell boundaries of the standard cell layout.

公开(公告)号：US20160358902A1

公开(公告)日：2016-12-08

申请号：US15243787

申请日：2016-08-22

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Tung-Heng Hsieh ,  Hui-Zhong Zhuang ,  Chung-Te Lin ,  Ting-Wei Chiang ,  Sheng-Hsiung Wang ,  Li-Chun Tien

IPC: H01L27/02 ,  H01L23/522 ,  H01L23/528 ,  H01L23/532

CPC classification number: H01L27/0207 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/5283 ,  H01L23/5286 ,  H01L23/53271 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An integrated circuit comprises a first layer on a first level. The first layer comprises a set of first lines. The first lines each have a length and a width. The length of each of the first lines is greater than the width. The integrated circuit also comprises a second layer on a second level different from the first level. The second layer comprises a set of second lines. The second lines each have a length and a width. The length of each of the second lines is greater than the width. The integrated circuit further comprises a coupling configured to connect at least one first line of the set of first lines with at least one second line of the set of second lines. The coupling has a length and a width. The set of second lines has a pitch measured between the lines of the set of second lines in the first direction. The length of the first coupling is greater than or equal to the pitch.

Abstract translation: 集成电路包括第一层上的第一层。 第一层包括一组第一行。 第一行各有一个长度和宽度。 第一行的长度大于宽度。 集成电路还包括与第一电平不同的第二电平的第二层。 第二层包括一组第二线。 第二行各有一个长度和一个宽度。 第二行的长度大于宽度。 集成电路还包括被配置为将该组第一线的至少一条第一线与该组第二线的至少一条第二线连接的耦合。 联轴器具有长度和宽度。 该组第二线具有在第一方向上的该组第二线的线之间测量的间距。 第一耦合的长度大于或等于音高。

公开(公告)号：US09431381B2

公开(公告)日：2016-08-30

申请号：US14500528

申请日：2014-09-29

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Tung-Heng Hsieh ,  Hui-Zhong Zhuang ,  Chung-Te Lin ,  Sheng-Hsiung Wang ,  Ting-Wei Chiang ,  Li-Chun Tien

IPC: G06F17/50 ,  H01L27/02

CPC classification number: H01L27/0207 ,  G06F17/5068 ,  G06F17/5072 ,  G06F17/5081 ,  H01L23/528 ,  H01L27/092

Abstract: A method of processing a gate electrode cutting (CUT) layout usable for fabricating an integrated circuit (IC) is disclosed. The method includes determining if a first CUT layout pattern and a second CUT layout pattern are in compliance with a predetermined spatial resolution requirement. If the first CUT layout pattern and the second CUT layout pattern are not in compliance with the predetermined spatial resolution requirement, a merged CUT layout pattern is generated based on the first CUT layout pattern, the second CUT layout pattern, and a stitching layout pattern, and a remedial connecting layout pattern is added to a conductive layer layout. The stitching layout pattern corresponds to a carved-out portion of a third gate electrode structure. The remedial connecting layout pattern corresponds to fabricating a conductive feature electrically connecting two portions of the third gate electrode structure that are separated by the corresponding carved-out portion.

Abstract translation: 公开了一种处理可用于制造集成电路（IC）的栅电极切割（CUT）布局的方法。 该方法包括确定第一CUT布局图案和第二CUT布局图案是否符合预定的空间分辨率要求。 如果第一CUT布局图案和第二CUT布局图案不符合预定的空间分辨率要求，则基于第一CUT布局图案，第二CUT布局图案和拼接布局图案来生成合并的CUT布局图案， 并且补丁连接布局图案被添加到导电层布局。 缝合布局图案对应于第三栅电极结构的雕刻部分。 补救连接布局图案对应于制造电连接第三栅电极结构的两个由相应的雕刻部分分隔的部分的导电特征。

公开(公告)号：US09105466B2

公开(公告)日：2015-08-11

申请号：US14084823

申请日：2013-11-20

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Lee-Chung Lu ,  Li-Chun Tien ,  Hui-Zhong Zhuang ,  Mei-Hui Huang

IPC: G06F17/50 ,  H01L27/02 ,  H01L27/118

CPC classification number: H01L27/0207 ,  G06F17/5068 ,  G06F17/5077 ,  H01L27/11807 ,  H01L2027/11875 ,  H01L2027/11885

Abstract: An integrated circuit includes a first standard cell over a substrate, a power rail, and a first connection plug. The first standard cell includes an active area, at least one gate electrode overlapping the active area of the first standard cell, and at least one metallic line structure overlapping the active area of the first standard cell. The at least one metallic line structure is substantially parallel to the gate electrode. The power rail is substantially orthogonal to the at least one metallic line structure of the first standard cell. The power rail overlaps the at least one metallic line structure of the first standard cell, and the power rail has a flat edge extending through the first standard cell. The first connection plug is at a region where the power rail overlaps the at least one metallic line structure of the first standard cell.

Abstract translation: 集成电路包括基板上的第一标准单元，电源导轨和第一连接插头。 第一标准单元包括有源区，与第一标准单元的有效区重叠的至少一个栅极，以及与第一标准单元的有源区重叠的至少一个金属线结构。 至少一个金属线结构基本上平行于栅电极。 电源轨基本上与第一标准单元的至少一个金属线结构正交。 电源轨道与第一标准单元的至少一个金属线结构重叠，并且电源轨具有延伸穿过第一标准单元的平坦边缘。 第一连接插头位于电源轨道与第一标准单元的至少一个金属线结构重叠的区域。

公开(公告)号：US09098668B2

公开(公告)日：2015-08-04

申请号：US14092697

申请日：2013-11-27

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Li-Chun Tien ,  Hui-Zhong Zhuang ,  Ting-Wei Chiang ,  Hsiang-Jen Tseng ,  Wei-Yu Chen

IPC: G06F17/50

CPC classification number: G06F17/5072 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A cell layout includes a first metal line for VDD power, which includes a first jog coupling to and being perpendicular to the first metal line. A second metal line is for VSS power, and includes a second jog coupling to and being perpendicular to the second metal line. The cell layout includes an upper cell boundary, a lower cell boundary, a first cell boundary and a second cell boundary. The upper cell boundary and the lower cell boundary extend along X direction. The first cell boundary and the second cell boundary extend along Y direction. The upper cell boundary is defined in a portion of the first metal line. The lower cell boundary is defined in a portion of the second metal line. The first cell boundary is defined in a portion of the first jog and a portion of the second jog.

Abstract translation: 电池布局包括用于VDD电力的第一金属线，其包括到第一金属线并且垂直于第一金属线的第一点动耦合。 第二金属线用于VSS电力，并且包括与第二金属线垂直的第二点动耦合。 单元布局包括上单元边界，下单元边界，第一单元边界和第二单元边界。 上单元边界和下单元边界沿着X方向延伸。 第一个单元边界和第二个单元边界沿Y方向延伸。 上电池边界限定在第一金属线的一部分中。 下部单元边界被限定在第二金属线的一部分中。 第一单元边界被限定在第一点动的一部分和第二点动的一部分中。

公开(公告)号：US20150149976A1

公开(公告)日：2015-05-28

申请号：US14092697

申请日：2013-11-27

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Li-Chun Tien ,  Hui-Zhong Zhuang ,  Ting-Wei Chiang ,  Hsiang-Jen Tseng ,  Wei-Yu Chen

IPC: G06F17/50

CPC classification number: G06F17/5072 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A cell layout includes a first metal line for VDD power, which includes a first jog coupling to and being perpendicular to the first metal line. A second metal line is for VSS power, and includes a second jog coupling to and being perpendicular to the second metal line. The cell layout includes an upper cell boundary, a lower cell boundary, a first cell boundary and a second cell boundary. The upper cell boundary and the lower cell boundary extend along X direction. The first cell boundary and the second cell boundary extend along Y direction. The upper cell boundary is defined in a portion of the first metal line. The lower cell boundary is defined in a portion of the second metal line. The first cell boundary is defined in a portion of the first jog and a portion of the second jog.

Abstract translation: 电池布局包括用于VDD电力的第一金属线，其包括到第一金属线并且垂直于第一金属线的第一点动耦合。 第二金属线用于VSS电力，并且包括与第二金属线垂直的第二点动耦合。 单元布局包括上单元边界，下单元边界，第一单元边界和第二单元边界。 上单元边界和下单元边界沿着X方向延伸。 第一个单元边界和第二个单元边界沿Y方向延伸。 上电池边界限定在第一金属线的一部分中。 下部单元边界被限定在第二金属线的一部分中。 第一单元边界被限定在第一点动的一部分和第二点动的一部分中。

公开(公告)号：US20150035070A1

公开(公告)日：2015-02-05

申请号：US13955796

申请日：2013-07-31

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Ting-Wei Chiang ,  Chun-Fu Chen ,  Hsiang-Jen Tseng ,  Wei-Yu Chen ,  Hui-Zhong Zhuang ,  Shang-Chih Hsieh ,  Li-Chun Tien

IPC: H01L27/092 ,  G06F17/50

CPC classification number: H01L27/092 ,  G06F17/5068 ,  H01L21/823437 ,  H01L27/0207 ,  H01L27/088

Abstract: An integrated circuit layout includes a first active region, a second active region, a first PODE (poly on OD edge), a second PODE, a first transistor and a second transistor. The first transistor, on the first active region, includes a gate electrode, a source region and a drain region. The second transistor, on the second active region, includes a gate electrode, a source region and a drain region. The first active region and the second active region are adjacent and electrically disconnected with each other. The first PODE and the second PODE are on respective adjacent edges of the first active region and the second active region. The source regions of the first and second transistor are adjacent with the first PODE and the second PODE respectively. The first PODE and the second PODE are sandwiched between source regions of the first transistor and the second transistor.

Abstract translation: 集成电路布局包括第一有源区，第二有源区，第一PODE（OD边缘上的poly），第二PODE，第一晶体管和第二晶体管。 在第一有源区上的第一晶体管包括栅电极，源极区和漏极区。 在第二有源区上的第二晶体管包括栅电极，源极区和漏极区。 第一有源区和第二有源区相邻并且彼此电断开。 第一PODE和第二PODE位于第一有源区和第二有源区的相邻相邻边缘上。 第一和第二晶体管的源极区分别与第一PODE和第二PODE相邻。 第一PODE和第二PODE夹在第一晶体管和第二晶体管的源极区之间。