公开(公告)号：US08015567B2

公开(公告)日：2011-09-06

申请号：US10931014

申请日：2004-08-31

Applicant: David T. Hass

Inventor： David T. Hass

IPC: G06F9/46 ,  G06F15/76 ,  G06F9/44 ,  G06F15/167 ,  G06F15/16 ,  H04L12/56

CPC classification number: H04L49/15 ,  G06F12/0813

Abstract: An advanced processor comprises a plurality of multithreaded processor cores each having a data cache and instruction cache. A data switch interconnect is coupled to each of the processor cores and configured to pass information among the processor cores. A messaging network is coupled to each of the processor cores and a plurality of communication ports. In one aspect of an embodiment of the invention, the data switch interconnect is coupled to each of the processor cores by its respective data cache, and the messaging network is coupled to each of the processor cores by its respective message station. Advantages of the invention include the ability to provide high bandwidth communications between computer systems and memory in an efficient and cost-effective manner.

Abstract translation: 高级处理器包括多个具有数据高速缓存和指令高速缓存的多线程处理器核心。 数据交换机互连耦合到每个处理器核并被配置为在处理器核之间传递信息。 消息传递网络耦合到每个处理器核和多个通信端口。 在本发明的实施例的一个方面，数据交换机互连通过其各自的数据高速缓存与每个处理器核心耦合，并且消息传递网络通过其相应的消息站耦合到每个处理器核心。 本发明的优点包括以有效和成本有效的方式在计算机系统和存储器之间提供高带宽通信的能力。

公开(公告)号：US07978709B1

公开(公告)日：2011-07-12

申请号：US12165541

申请日：2008-06-30

Applicant: Srinivasan Venkatachary ,  Pankaj Gupta

Inventor： Srinivasan Venkatachary ,  Pankaj Gupta

IPC: H04L12/28

CPC classification number: H04L45/00 ,  H04L45/54 ,  H04L45/7453

Abstract: A method of constructing a hierarchical database from an initial plurality of rules. A first rule of the initial plurality of rules is added to: a first sub-database if a first bit of the rule is a logic ‘0’ value; a second sub-database if the first bit is a logic ‘1’ value; or a third sub-database if the first bit is in a masked state, ‘X’, indicating that the first bit may be either a logic ‘1’ or a logic ‘0’ value.

Abstract translation: 一种从初始多个规则构建分层数据库的方法。 如果规则的第一位是逻辑“0”值，则将初始多个规则的第一规则添加到：第一子数据库; 第二个子数据库，如果第一个位是逻辑“1”值; 或第三子数据库，如果第一位处于屏蔽状态'X'，表示第一位可以是逻辑'1'或逻辑'0'值。

公开(公告)号：US07969758B2

公开(公告)日：2011-06-28

申请号：US12211565

申请日：2008-09-16

Applicant: Sunder Rathnavelu Raj

Inventor： Sunder Rathnavelu Raj

IPC: G11C15/00

CPC classification number: G11C15/00 ,  G06F17/30985 ,  Y10S707/99932 ,  Y10S707/99933 ,  Y10S707/99943 ,  Y10S707/99945 ,  Y10S707/99948

Abstract: Disclosed herein is a method and apparatus for multiple string searching using a ternary content addressable memory. The method includes receiving a text string having a plurality of characters and performing an unanchored search of a database of stored patterns matching one or more characters of the text string using a state machine, wherein the state machine comprises a ternary content addressable memory (CAM) and wherein the performing comprises comparing a state and one of the plurality of characters with contents of a state field and a character field, respectively, stored in the ternary CAM. In the method and apparatus described herein, one or more of the following search features may be supported: exact string matching, inexact string matching, single character wildcard matching, multiple character wildcard matching, case insensitive matching, parallel matching and rollback.

Abstract translation: 本文公开了一种使用三进制内容可寻址存储器进行多字符串搜索的方法和装置。 该方法包括接收具有多个字符的文本串，并且使用状态机执行与文本串的一个或多个字符匹配的存储模式的数据库的非存储搜索，其中，所述状态机包括三元内容可寻址存储器（CAM） 并且其中所述执行包括将所述多个字符中的状态和所述一个字符分别与存储在所述三元CAM中的状态字段和字符字段的内容进行比较。 在本文描述的方法和装置中，可以支持以下搜索特征中的一个或多个：精确字符串匹配，不精确字符串匹配，单字符通配符匹配，多字符通配符匹配，不区分大小写匹配，并行匹配和回滚。

公开(公告)号：US07945823B2

公开(公告)日：2011-05-17

申请号：US11713258

申请日：2007-03-02

Applicant: Ramesha Doddamane ,  Eswar Vadlamani ,  Gopalakrishnan Perur Krishnan ,  Tarjinder Singh

Inventor： Ramesha Doddamane ,  Eswar Vadlamani ,  Gopalakrishnan Perur Krishnan ,  Tarjinder Singh

IPC: G11C29/00

CPC classification number: G11C29/18 ,  G11C15/00 ,  G11C29/16 ,  G11C29/44 ,  G11C2029/1208 ,  G11C2029/3602

Abstract: A built-in self-test (BIST) circuit for testing addressable locations can include a BIST generator (202) that can generate test addresses for testing each addressable location. Defective addresses can be stored in a fault address store (216). An address range selector circuit (230) can limit the range of addresses generated by an address generator (234). Once defective addresses for a first range have been detected, an address range selector circuit (230) can test another range. An entire address range can thus be tested regardless of the depth of a fault address store (216).

Abstract translation: 用于测试可寻址位置的内置自检（BIST）电路可以包括可以生成用于测试每个可寻址位置的测试地址的BIST发生器（202）。 有缺陷的地址可以存储在故障地址存储区（216）中。 地址范围选择器电路（230）可以限制由地址发生器（234）产生的地址范围。 一旦已经检测到第一范围的有缺陷的地址，地址范围选择器电路（230）可以测试另一范围。 因此，无论故障地址存储（216）的深度如何，都可以测试整个地址范围。

公开(公告)号：US07941603B2

公开(公告)日：2011-05-10

申请号：US12627915

申请日：2009-11-30

Applicant: David T. Hass

Inventor： David T. Hass

IPC: G06F12/00 ,  G06F15/173

CPC classification number: H04L49/00 ,  G06F12/0813 ,  H04L49/30

Abstract: An advanced processor comprises a plurality of multithreaded processor cores each having a data cache and instruction cache. A data switch interconnect is coupled to each of the processor cores and configured to pass information among the processor cores. A messaging network is coupled to each of the processor cores and a plurality of communication ports. In one aspect of an embodiment of the invention, the data switch interconnect is coupled to each of the processor cores by its respective data cache, and the messaging network is coupled to each of the processor cores by its respective message station. Advantages of the invention include the ability to provide high bandwidth communications between computer systems and memory in an efficient and cost-effective manner.

Abstract translation: 高级处理器包括多个具有数据高速缓存和指令高速缓存的多线程处理器核心。 数据交换机互连耦合到每个处理器核并被配置为在处理器核之间传递信息。 消息传递网络耦合到每个处理器核和多个通信端口。 在本发明的实施例的一个方面，数据交换机互连通过其各自的数据高速缓存与每个处理器核心耦合，并且消息传递网络通过其相应的消息站耦合到每个处理器核心。 本发明的优点包括以有效和成本有效的方式在计算机系统和存储器之间提供高带宽通信的能力。

公开(公告)号：US07933282B1

公开(公告)日：2011-04-26

申请号：US11935270

申请日：2007-11-05

Applicant: Pankaj Gupta ,  Liao Wei-Cherng

Inventor： Pankaj Gupta ,  Liao Wei-Cherng

IPC: H04L12/56

CPC classification number: G06F17/30982

Abstract: A packet classification device includes a CAM device, an SRAM device, and a control circuit that controls and coordinates the operations of the CAM and SRAM devices. For some embodiments, a first CAM block stores unique entries for each packet header field, a RAM block coupled to the first CAM block stores field labels for the unique packet header fields, a second CAM block stores group labels consisting of unique combinations of concatenated field labels, and a second RAM block coupled to the second CAM block stores a group identification (ID) for each group label, wherein each group ID identifies a corresponding one of the groups of rules.

Abstract translation: 分组分类装置包括CAM装置，SRAM装置和控制和协调CAM和SRAM装置的操作的控制电路。 对于一些实施例，第一CAM块存储每个分组报头字段的唯一条目，耦合到第一CAM块的RAM块存储用于唯一分组报头字段的字段标签，第二CAM块存储由连接字段的唯一组合组成的组标签 标签和耦合到第二CAM块的第二RAM块存储每个组标签的组标识（ID），其中每个组ID标识规则组中的相应一个组。

公开(公告)号：US07919991B1

公开(公告)日：2011-04-05

申请号：US12499771

申请日：2009-07-08

Applicant: Sachin Joshi

Inventor： Sachin Joshi

IPC: G01R29/00 ,  H03D3/00 ,  H03D9/00

CPC classification number: H03K5/26 ,  H03K19/018528

Abstract: A comparator circuit is disclosed that determines whether a first binary value is greater than, equal to, and/or less than a second binary value without employing binary adder circuits, and therefore is simpler, occupies less circuit area, and consumes less power than conventional comparator circuits having binary adders. For some embodiments, the comparator circuit is capable of performing full comparison operations on two or more arbitrary binary values. The comparator circuit can be implemented in TCAM devices to perform regular expression search operations.

Abstract translation: 公开了一种比较器电路，其在不使用二进制加法器电路的情况下确定第一二进制值是否大于，等于和/或小于第二二进制值，因此更简单，占用更少的电路面积，并且消耗的功率比常规 具有二进制加法器的比较器电路。 对于一些实施例，比较器电路能够对两个或更多个任意二进制值执行完全比较操作。 比较器电路可以在TCAM设备中实现，以执行正则表达式搜索操作。

公开(公告)号：US07917486B1

公开(公告)日：2011-03-29

申请号：US11689429

申请日：2007-03-21

Applicant: Pankaj Gupta ,  Srinivasan Venkatachary

Inventor： Pankaj Gupta ,  Srinivasan Venkatachary

IPC: G06F7/00 ,  G06F17/30

CPC classification number: G06F17/30985 ,  H04L63/1416 ,  Y10S707/99932 ,  Y10S707/99936 ,  Y10S707/99942

Abstract: A search tree embodying a plurality of signatures to be compared with an input string of characters and including a number of branches of sequential states originating at a root node, wherein each state comprises a state entry including a failure transition and one or more success transitions, is optimized by selecting a failure size parameter indicating a minimum number of characters to be traversed on the failure transitions and selectively modifying the search tree to create a modified search tree for which all failure transitions to non-root states are characterized by the selected failure size parameter.

Abstract translation: 体现多个签名的搜索树，其将与输入的字符串进行比较，并且包括源于根节点的顺序状态的多个分支，其中每个状态包括包括故障转移和一个或多个成功转换的状态输入， 通过选择故障大小参数来指示在故障转移上要穿过的最少字符数量并选择性地修改搜索树以创建修改的搜索树来优化，所述修改的搜索树对于所有失败转换到非根状态的特征在于所选择的故障大小 参数。

公开(公告)号：US07881090B2

公开(公告)日：2011-02-01

申请号：US12405154

申请日：2009-03-16

Applicant: Kee Park

Inventor： Kee Park

IPC: G11C15/00

CPC classification number: G11C15/04

Abstract: A read operation and a search operation are performed during the same cycle within a CAM system including a CAM array by: (1) forcing a non-matching condition to exist in the row of the CAM array selected for the read operation, (2) comparing the read data value with the search data value outside of the CAM array to determine whether a match exists, and (3) prioritizing the results of the search operation performed within the CAM array and the results of the comparison performed outside of the CAM array to provide a final search result.

Abstract translation: 在包括CAM阵列的CAM系统内的同一周期内，通过以下操作来执行读操作和搜索操作：（1）强制非匹配条件存在于为读操作选择的CAM阵列的行中，（2） 将读取的数据值与CAM阵列外部的搜索数据值进行比较以确定是否存在匹配，以及（3）对CAM阵列内执行的搜索操作的结果进行优先级排序，以及在CAM阵列外执行的比较结果 以提供最终的搜索结果。

公开(公告)号：US20100318763A1

公开(公告)日：2010-12-16

申请号：US12859013

申请日：2010-08-18

Applicant: Gaurav SINGH ,  Dave HASS ,  Daniel CHEN

Inventor： Gaurav SINGH ,  Dave HASS ,  Daniel CHEN

IPC: G06F12/10 ,  G06F12/00

CPC classification number: G06F12/1027 ,  Y02D10/13

Abstract: Extended translation look-aside buffers (eTLB) for converting virtual addresses into physical addresses are presented, the eTLB including, a physical memory address storage having a number of physical addresses, a virtual memory address storage configured to store a number of virtual memory addresses corresponding with the physical addresses, the virtual memory address storage including, a set associative memory structure (SAM), and a content addressable memory (CAM) structure; and comparison circuitry for determining whether a requested address is present in the virtual memory address storage, wherein the eTLB is configured to receive an index register for identifying the SAM structure and the CAM structure, and wherein the eTLB is configured to receive an entry register for providing a virtual page number corresponding with the plurality of virtual memory addresses.

Abstract translation: 呈现用于将虚拟地址转换成物理地址的扩展翻译后备缓冲器（eTLB），eTLB包括具有多个物理地址的物理存储器地址存储器，虚拟存储器地址存储器，被配置为存储对应的多个虚拟存储器地址 物理地址，虚拟存储器地址存储包括集合关联存储器结构（SAM）和内容可寻址存储器（CAM）结构; 以及用于确定所请求的地址是否存在于所述虚拟存储器地址存储器中的比较电路，其中所述eTLB被配置为接收用于识别所述SAM结构和所述CAM结构的索引寄存器，并且其中所述eTLB被配置为接收用于 提供与所述多个虚拟存储器地址对应的虚拟页码。