公开(公告)号：US20060104144A1

公开(公告)日：2006-05-18

申请号：US11169949

申请日：2005-06-30

Applicant: Sang Byeon ,  Kee Park

Inventor： Sang Byeon ,  Kee Park

IPC: G11C5/14

CPC classification number: G11C5/14

Abstract: A semiconductor memory device generates a control signal for regulating a potential of an internal power voltage when an extended mode register is set to adjust an operating speed and a tWR (time to write recovery) of a chip. The semiconductor memory device comprises an extended mode register setting unit and an internal power voltage generating unit. When an internal circuit enters into a specific mode for high-speed operation, the extended mode register setting unit outputs a plurality of internal power control signals to regulate a potential of an internal power voltage of the internal circuit. The internal power voltage generating unit generates an internal power voltage by regulating the potential of the internal power voltage in response to the plurality of internal power control signals.

Abstract translation: 当扩展模式寄存器被设置以调整芯片的操作速度和tWR（写入恢复时间）时，半导体存储器件产生用于调节内部电源电压的电位的控制信号。 半导体存储器件包括扩展模式寄存器设置单元和内部电源电压产生单元。 当内部电路进入用于高速运行的特定模式时，扩展模式寄存器设置单元输出多个内部功率控制信号以调节内部电路的内部电源电压的电位。 内部电力电压产生单元通过响应于多个内部功率控制信号调节内部电力电压的电位而产生内部电力电压。

公开(公告)号：US06975527B1

公开(公告)日：2005-12-13

申请号：US10293176

申请日：2002-11-12

Applicant: Kee Park

Inventor： Kee Park

IPC: G11C5/06 ,  G11C8/00

CPC classification number: G11C5/063 ,  G11C7/1045

Abstract: A number of memory array units are placed on a die. Each memory array within a unit is coupled to a channel that includes one or more data lines coupled to a pad on the die. Each memory array unit utilizes a different channel. Memory array units are grouped together in pairs on the die to form memory array groups. The two channels of each memory array group form boundaries on the die. The pads coupled to each channel of a memory array group are positioned within those boundaries. The pads may be arranged such that the same pad layout can be used across different dies fabricated for use at different bus widths. In one embodiment, a set of the pads are used in applications where the die is configured for a first bus width and a portion of the pads used in the first bus width applications are not used in applications where the die is configured to for a second bus width. By providing additional pads, the die may be connected to external leads in different bus width configurations and with different external lead sequences without substantially increasing the length of the internal data bus.

Abstract translation: 多个存储器阵列单元放置在管芯上。 单元内的每个存储器阵列耦合到包括耦合到管芯上的焊盘的一个或多个数据线的沟道。 每个存储器阵列单元利用不同的通道。 存储器阵列单元成对地分组在管芯上以形成存储器阵列组。 每个存储器阵列组的两个通道在芯片上形成边界。 耦合到存储器阵列组的每个通道的焊盘定位在这些边界内。 垫可以被布置成使得可以在制造用于不同总线宽度的不同模具上使用相同的垫布局。 在一个实施例中，一组焊盘用于其中管芯被配置为第一总线宽度的应用中，并且在第一总线宽度应用中使用的焊盘的一部分不用于其中管芯被配置为第二 总线宽度。 通过提供附加的焊盘，芯片可以以不同的总线宽度配置和不同的外部引线序列连接到外部引线，而基本上不增加内部数据总线的长度。

公开(公告)号：US06937491B2

公开(公告)日：2005-08-30

申请号：US10263223

申请日：2002-10-02

Applicant: Kee Park ,  Scott Yu-Fan Chu

Inventor： Kee Park ,  Scott Yu-Fan Chu

IPC: G11C15/00

CPC classification number: G11C15/00

Abstract: Content addressable memory (CAM) devices use both hard and soft priority techniques to allocate entries of different priority therein. The priorities of multiple CAM array blocks within the CAM device may be programmed before or as entries are loaded therein and may be reprogrammed during operation as the allocation of entries within the CAM device changes. The allocation of entries may change in response to additions or deletions of entries or as entries are reprioritized. The CAM devices include preferred priority resolution circuits that can resolve competing soft and hard priorities between multiple hit signals that are generated in response to a search operation. Such hit signals may be active to reflect the presence of at least one matching entry within a CAM array block. The resolution of which active hit signal has the highest overall priority among many can be used to facilitate the identification of the location (e.g., array address and row address) of a highest priority matching entry within the entire CAM device. A priority resolution circuit may also resolve competing hard priorities between two or more active hit signals having equivalent soft priority. This aspect of the priority resolution circuit is provided so that an active hit signal having a highest overall priority can be resolved whenever multiple CAM array blocks having the same soft priority are detected as having matching entries therein during a search operation.

Abstract translation: 内容可寻址存储器（CAM）设备使用硬和软优先级技术来分配不同优先级的条目。 CAM设备内的多个CAM阵列块的优先级可以在条目加载之前被编程，也可以在操作期间被重新编程，因为CAM设备内的条目的分配改变。 条目的分配可能会随着条目的添加或删除而变化，或者条目被重新设定为优先级。 CAM设备包括优选的优先级分辨率电路，其可以解决响应于搜索操作而产生的多个命中信号之间的竞争的软和硬优先级。 这种命中信号可以是有效的，以反映CAM阵列块内至少一个匹配条目的存在。 可以使用哪个主动命中信号具有最高总体优先级的分辨率在许多之中，以便于识别整个CAM设备内的最高优先级匹配条目的位置（例如，阵列地址和行地址）。 优先级分辨率电路还可以解决具有相同软优先级的两个或更多个激活命中信号之间的竞争硬优先级。 提供优先级分辨率电路的这个方面，使得每当具有相同软优先级的每个CAM阵列块在搜索操作期间被检测为具有匹配条目时，可以解决具有最高总优先级的主动命中信号。

公开(公告)号：US20050152199A1

公开(公告)日：2005-07-14

申请号：US10921760

申请日：2004-08-18

Applicant: Kee Park ,  Robert Proebsting

Inventor： Kee Park ,  Robert Proebsting

IPC: G11C7/18 ,  G11C15/04 ,  G11C5/00

CPC classification number: G11C7/18 ,  G11C11/405 ,  G11C11/406 ,  G11C11/4097 ,  G11C15/043

Abstract: A CAM cell is disclosed that includes a comparator and two three-transistor (3T) DRAM cells connected to a pair of associated bit lines. Data is stored using intrinsic capacitance of each 3T DRAM cell, and is applied to the gate terminal of a pull-down transistor of the comparator. During refresh operations, inverted data values are written onto the bit lines, and subsequently written from the bit lines to the 3T DRAM cells. In ternary embodiments, an inverting refresh circuit is used to re-invert the inverted data values prior to being written to the 3T DRAM cells. In one embodiment, the 3T DRAM cells are cross-coupled to the bit lines, and the inverting refresh circuit transfers bits from one bit line to the other.

Abstract translation: 公开了一种CAM单元，其包括比较器和连接到一对相关位线的两个三晶体管（3T）DRAM单元。 使用每个3T DRAM单元的固有电容存储数据，并将其施加到比较器的下拉晶体管的栅极端子。 在刷新操作期间，将反相数据值写入位线，然后从位线写入3T DRAM单元。 在三元实施例中，反相刷新电路用于在被写入3T DRAM单元之前重新反转反相数据值。 在一个实施例中，3T DRAM单元被交叉耦合到位线，并且反相刷新电路将位从一个位线传输到另一位。

公开(公告)号：US06900999B1

公开(公告)日：2005-05-31

申请号：US10609756

申请日：2003-06-30

Applicant: Ting-Pwu Yen ,  Kee Park

Inventor： Ting-Pwu Yen ,  Kee Park

IPC: G11C15/04

CPC classification number: G11C15/04

Abstract: Ternary CAM cells are provided that have extremely small layout footprint size and efficient layout aspect ratios that enhance scalability. The cells also have high degrees of symmetry that facilitate high yield interconnections to bit, data and match lines. A 16T ternary CAM cell includes first and second pairs of access transistors that extend adjacent a first side of the cell, and first and second pairs of cross-coupled inverters that extend adjacent a second side of the cell. First and second halves of a 4T compare circuit are also provided. The first half of the 4T compare circuit is positioned so that is extends between the first pair of access transistors and the first pair of cross-coupled inverters. Similarly, the second half of the 4T compare circuit is positioned so that it extends between the second pair of access transistors and the second pair of cross-coupled inverters.

Abstract translation: 提供三进制CAM单元，其具有非常小的布局尺寸和有效的布局纵横比，从而提高可扩展性。 这些单元还具有高度的对称性，可以实现位，数据和匹配线的高产出互连。 16T三元CAM单元包括在单元的第一侧附近延伸的第一和第二对存取晶体管，以及在单元的第二面附近延伸的第一和第二对交叉耦合的反相器。 还提供了4T比较电路的第一和第二半。 定位4T比较电路的前半部分，使其在第一对存取晶体管和第一对交叉耦合的反相器之间延伸。 类似地，4T比较电路的第二半被定位成使得其在第二对存取晶体管和第二对交叉耦合的反相器之间延伸。

公开(公告)号：US06879532B1

公开(公告)日：2005-04-12

申请号：US10934209

申请日：2004-09-03

Applicant: Robert J. Proebsting ,  Scott Yu-Fan Chu ,  Kee Park

Inventor： Robert J. Proebsting ,  Scott Yu-Fan Chu ,  Kee Park

IPC: G11C15/00 ,  G11C7/00

CPC classification number: G11C15/00

Abstract: Content addressable memory (CAM) devices include at least one CAM array that is configured to identify at least one match between a new search word and entries therein by performing a staged compare operation that conserves bit line power by initially floating at least some of a plurality of bit lines in said CAM array and then driving the at least some of a plurality of bit lines with second bits of the new search word in response to detecting at least one partial match between first bits of the new search word and the entries in said CAM array.

Abstract translation: 内容可寻址存储器（CAM）设备包括至少一个CAM阵列，其被配置为通过执行通过初始漂移多个的至少一些来暂时保持位线功率的分级比较操作来识别新的搜索词与其中的条目之间的至少一个匹配 并且然后响应于检测到新搜索词的第一位与所述新搜索词中的条目之间的至少一个部分匹配而在新搜索词的第二位中驱动多个位线中的至少一些位线 CAM阵列。

公开(公告)号：US07692941B2

公开(公告)日：2010-04-06

申请号：US12197549

申请日：2008-08-25

Applicant: Scott Chu ,  Kee Park

Inventor： Scott Chu ,  Kee Park

IPC: G11C15/00

CPC classification number: G11C29/02 ,  G11C5/147 ,  G11C15/00 ,  G11C29/021 ,  G11C29/028

Abstract: A CAM system includes an integrated circuit chip having: logic & control circuitry, a CAM cell array, read/write access circuitry that performs read and write accesses to the CAM cell array, comparison access circuitry that performs comparison operations to the CAM cell array, a first voltage supply pad coupled to the read/write access circuitry; and a second voltage supply pad coupled to the comparison access circuitry. A first voltage supply, external to the integrated circuit chip, provides a first supply voltage to the first voltage supply pad, wherein the logic & control circuitry is powered by the first supply voltage. A second voltage supply, external to the integrated circuit chip, provides a second supply voltage to the second voltage supply pad, wherein at least a portion of the comparison access circuitry is powered by the second supply voltage, wherein the second supply voltage is less than the first supply voltage.

Abstract translation: CAM系统包括具有逻辑和控制电路，CAM单元阵列，对CAM单元阵列执行读和写访问的读/写访问电路的集成电路芯片，对CAM单元阵列执行比较操作的比较访问电路， 耦合到所述读/写访问电路的第一电压供应焊盘; 以及耦合到所述比较访问电路的第二电压供给焊盘。 集成电路芯片外部的第一电压源向第一电压供应焊盘提供第一电源电压，其中逻辑和控制电路由第一电源电压供电。 集成电路芯片外部的第二电压源为第二电压供应焊盘提供第二电源电压，其中至少一部分比较存取电路由第二电源电压供电，其中第二电源电压小于 第一电源电压。

公开(公告)号：US07471537B1

公开(公告)日：2008-12-30

申请号：US11751900

申请日：2007-05-22

Applicant: Kee Park

Inventor： Kee Park

IPC: G11C15/00

CPC classification number: G11C15/04

Abstract: A content addressable memory array includes a plurality of rows of active CAM cells electrically coupled to a corresponding plurality of active match lines and at least one row of dummy cells, which are configured to generate an always-match condition on a dummy match line when the CAM array is undergoing a search operation. A match line pull-up circuit is provided. This match line pull-up circuit is electrically coupled to the plurality of active match lines and the dummy match line. The pull-up circuit is responsive to a calibration control signal that sets a pull-up strength of the match line pull-up circuit when the CAM array is undergoing the search operation. A sense amplifier, which is coupled to the match lines, includes a control circuit configured to adjust the calibration control signal in response to evaluating a first voltage on the dummy match line relative to a reference voltage.

Abstract translation: 内容可寻址存储器阵列包括电耦合到对应的多个有源匹配线和至少一行虚设单元的多行有源CAM单元，其被配置为在虚拟匹配线上产生始终匹配条件 CAM阵列正在进行搜索操作。 提供了匹配线上拉电路。 该匹配线上拉电路电耦合到多个有源匹配线和虚拟匹配线。 上拉电路响应于当CAM阵列正在进行搜索操作时设置匹配线上拉电路的上拉强度的校准控制信号。 耦合到匹配线的感测放大器包括控制电路，其被配置为响应于评估虚拟匹配线上相对于参考电压的第一电压来调整校准控制信号。

公开(公告)号：US20070275082A1

公开(公告)日：2007-11-29

申请号：US10570564

申请日：2004-09-03

Applicant: Hee Lee ,  Sung Kim ,  Jung Kim ,  Young Jung ,  Jung Kim ,  Ho Choi ,  Seung Chang ,  Kee Park

Inventor： Hee Lee ,  Sung Kim ,  Jung Kim ,  Young Jung ,  Jung Kim ,  Ho Choi ,  Seung Chang ,  Kee Park

IPC: A61K38/09 ,  A61K9/16

CPC classification number: A61K9/1647 ,  A61K9/1682 ,  A61K9/1694 ,  A61K38/09

Abstract: Disclosed is a method of preparing sustained release microspheres by spray-drying liquids with different compositions for preparation the sustained release microspheres through an ultrasonic dual-feed nozzle. Unlike conventional methods of preparing sustained release microspheres by spray-drying a single liquid containing a biodegradable polymer, a drug, an additive and a solvent through a single-feed nozzle, the present method is characterized by simultaneously spray-drying two liquids with different compositions for preparation of the sustained release microspheres respectively through internal and external channels of an ultrasonic dual-feed nozzle to coat sprayed droplets through the internal channel with other sprayed droplets through the external channel. The present method is effective in achieving a low initial release and a desired continuous release.

Abstract translation: 公开了一种通过喷雾干燥具有不同组成的液体制备缓释微球的方法，用于通过超声波双重给料喷嘴制备缓释微球。 与通过单一进料喷嘴喷雾干燥含有可生物降解的聚合物，药物，添加剂和溶剂的单一液体制备缓释微球体的常规方法不同，本方法的特征在于同时喷雾干燥具有不同组成的两种液体 分别通过超声双馈喷嘴的内部和外部通道制备缓释微球，通过内部通道将喷雾的液滴通过外部通道与其他喷雾液滴一起涂覆。 本发明的方法在实现低的初始释放和期望的连续释放方面是有效的。

公开(公告)号：US20070097483A1

公开(公告)日：2007-05-03

申请号：US11590753

申请日：2006-11-01

Applicant: Kee Park

Inventor： Kee Park

IPC: G02F1/153

CPC classification number: G02F1/155 ,  G02F2001/1555 ,  G02F2001/1635

Abstract: Disclosed is an electrochromic device including at least one display region and at least one non-display region, which are separated from each other, the electrochromic device including a first substrate, a first electrode, an electrochromic layer, an electrolyte layer, optionally an ion storage layer, a second electrode, and a second substrate, which are sequentially formed, wherein the ion storage layer and/or the second electrode are patterned so as to prevent the ion storage layer and/or the second electrode from existing in part or all of said at least one display region; and a display device including the electrochromic device. In the electrochromic device, only the second substrate and electrolyte layer are located between the observer and the electrochromic layer, so that it is possible to prevent a contrast ratio from being degraded due to the ion storage layer and/or second electrode.

Abstract translation: 公开了一种电致变色装置，其包括彼此分离的至少一个显示区域和至少一个非显示区域，该电致变色装置包括第一基板，第一电极，电致变色层，电解质层，任选的离子 存储层，第二电极和第二基板，其中图案化离子存储层和/或第二电极以防止离子存储层和/或第二电极部分或全部存在 的所述至少一个显示区域; 以及包括该电致变色装置的显示装置。 在电致变色装置中，仅第二基板和电解质层位于观察者和电致变色层之间，从而可以防止由于离子存储层和/或第二电极而引起的对比度降低。