公开(公告)号：US07187774B2

公开(公告)日：2007-03-06

申请号：US10147436

申请日：2002-05-15

Applicant: Tahir Rashid

Inventor： Tahir Rashid

IPC: H04B15/00

CPC classification number: H03G3/345 ,  H03G3/34

Abstract: A mute switch including a field effect transistor receiving a mute control signal at its gate for selectively supplying an audio signal from an input node to an output node. A bipolar transistor is connected between the input node and the FET for reducing the voltage level of the audio signal prior to its application to the input node, and a further bipolar transistor is connected between the FET and the output node for raising the voltage level of the audio signal prior to its application to the output node. This serves to maintain the DC bias level of the audio output signal independently of the status of the mute control signal.

Abstract translation: 一种静音开关，包括场效应晶体管，在其栅极处接收静音控制信号，用于选择性地将音频信号从输入节点提供给输出节点。 双极晶体管连接在输入节点和FET之间，用于在施加到输入节点之前降低音频信号的电压电平，并且在FET和输出节点之间连接另外的双极晶体管，以提高电压电平 该音频信号在其应用于输出节点之前。 这用于独立于静音控制信号的状态来维持音频输出信号的DC偏置电平。

公开(公告)号：US07170512B2

公开(公告)日：2007-01-30

申请号：US10133971

申请日：2002-04-26

Applicant: Trefor Southwell ,  Magne Sandven

Inventor： Trefor Southwell ,  Magne Sandven

IPC: G06T17/00

CPC classification number: G06T15/005

Abstract: A graphic processor having an index processing unit for pre-processing a list of vertices making up a three-dimensional image. The method of pre-processing comprising the following steps. First, decomposing the three-dimensional image into a plurality of primitive elements each defined by a set of vertices, each vertex comprising vertex information stored in a vertex storage area and addressable by a vertex index. Then receiving said vertex indices and creating a set of unique indices identifying a batch of vertices and loading only the vertices corresponding to said unique indices into the vertex storage area. Finally creating transformed primitive elements from transformed vertex information addressed in the vertex storage area using the unique indices.

Abstract translation: 一种具有索引处理单元的图形处理器，用于预处理构成三维图像的顶点列表。 预处理方法包括以下步骤。 首先，将三维图像分解为由一组顶点定义的多个基元，每个顶点包含存储在顶点存储区域中并且可由顶点索引寻址的顶点信息。 然后接收所述顶点索引并创建一组唯一索引，其识别一批顶点，并仅将与所述唯一索引对应的顶点加载到顶点存储区域中。 最后使用独特的索引从顶点存储区域中寻址的变换顶点信息创建变换的原始元素。

公开(公告)号：US07167887B2

公开(公告)日：2007-01-23

申请号：US10291218

申请日：2002-11-08

Applicant: Tariq Kurd

Inventor： Tariq Kurd

IPC: G06F7/38 ,  G06F7/52

CPC classification number: G06F7/535 ,  G06F7/5525

Abstract: The invention provides circuitry for carrying out a square root operation and a division operation. The circuitry utilizes common iteration circuitry for carrying out a plurality of iterations and means for identifying if an square root operation or a division operation is to be performed. The iteration circuitry is controlled in accordance with whether a square root or division operation is to be performed.

Abstract translation: 本发明提供了用于执行平方根操作和分割操作的电路。 该电路利用公共迭代电路进行多个迭代，以及用于识别是否要执行平方根操作或除法运算的装置。 根据是否要执行平方根或除法运算来控制迭代电路。

公开(公告)号：US07165199B2

公开(公告)日：2007-01-16

申请号：US11015330

申请日：2004-12-17

Applicant: Robert Warren

Inventor： Robert Warren

IPC: G01R31/28

CPC classification number: G01R31/318563 ,  G01R31/318536

Abstract: An integrated circuit comprising (i) a plurality of portions, each portion including test control circuitry; and (ii) at least one test input arranged to receive test data, wherein the test data is clocked in a plurality of time slots, with test data for different ones of the plurality of portions being allocated to different time slots.

Abstract translation: 一种集成电路，包括（i）多个部分，每个部分包括测试控制电路; 和（ii）布置成接收测试数据的至少一个测试输入，其中所述测试数据在多个时隙中计时，所述多个部分中的不同部分的测试数据被分配给不同的时隙。

公开(公告)号：US07155707B2

公开(公告)日：2006-12-26

申请号：US09977048

申请日：2001-10-12

Applicant: Stephen Clarke

Inventor： Stephen Clarke

IPC: G06F9/45 ,  G06F9/44

CPC classification number: G06F8/4451

Abstract: This patent describes a method of compiling a computer program from a sequence of computer instructions including a plurality of first, set branch, instructions which each identify a target address for a branch and a plurality of associated second, effect branch instructions which each implement a branch to a target address. The method comprising the steps of; reading the computer instructions in blocks; defining a set of target registers associated with each block for holding target addresses for the set branch instructions in that block; defining as a live range of blocks a set of blocks for which a target address of a particular set branch instruction is in a live state; and using the set of target registers and the live range to ensure that target registers holding target addresses in a live state are not available for other uses.

公开(公告)号：US07134058B2

公开(公告)日：2006-11-07

申请号：US09954638

申请日：2001-09-14

Applicant: Christophe Lauga

Inventor： Christophe Lauga

IPC: G11C29/00

CPC classification number: G11C29/30

Abstract: A semiconductor integrated circuit comprises a plurality of combinational logic components, a memory and a testing arrangement for configuring the memory prior to testing the combinational logic components using one or more scan chains. The arrangement includes a bit pattern generator for generating a predetermined bit pattern for writing to the memory, a switching arrangement for selectively switching the memory input to receive data from the combinational logic components or from the data generator. The switching arrangement and data generator are arranged to input the predetermined bit pattern to the memory prior to testing the integrated circuit.

Abstract translation: 半导体集成电路包括多个组合逻辑组件，存储器和用于在使用一个或多个扫描链测试组合逻辑组件之前配置存储器的测试装置。 该装置包括用于产生用于向存储器写入的预定位模式的位模式发生器，用于选择性地切换存储器输入以从组合逻辑组件或从数据发生器接收数据的切换装置。 开关布置和数据发生器被布置成在测试集成电路之前将预定的位模式输入到存储器。

公开(公告)号：US20060248486A1

公开(公告)日：2006-11-02

申请号：US11372235

申请日：2006-03-09

Applicant: Paul Barnes

Inventor： Paul Barnes

IPC: G06F17/50

CPC classification number: G06F17/5045 ,  G06F17/5068

Abstract: A method of designing a clock distribution network in an integrated circuit, the method including: creating a clock distribution network with all cells having a maximum drive strength; supplying parameters of the clock distribution network to a timing analysis tool; in the timing analysis tool, analyzing the timing of the clock distribution network in an iterative process including manipulating the drive strength of at least one cell in the clock distribution network and assessing whether there is an improvement in the timing, wherein the iterative process ceases where there is no improvement in the timing; and outputting a list of cells for which the drive strength was changed.

Abstract translation: 一种在集成电路中设计时钟分配网络的方法，所述方法包括：创建具有最大驱动强度的所有小区的时钟分配网络; 将时钟分配网络的参数提供给定时分析工具; 在时序分析工具中，在迭代过程中分析时钟分配网络的时序，包括操纵时钟分配网络中的至少一个小区的驱动强度，并评估是否有改进的时序，其中迭代过程停止在哪里 时间没有改善; 并输出驱动强度变化的单元的列表。

公开(公告)号：US20060245381A1

公开(公告)日：2006-11-02

申请号：US11303638

申请日：2005-12-16

Applicant: Donald Baxter ,  Brian Laffoley ,  J. Hurwitz

Inventor： Donald Baxter ,  Brian Laffoley ,  J. Hurwitz

IPC: H04L5/16

CPC classification number: G06F13/4265

Abstract: The data communication system includes a first control device, a second data device and a data link, including a first transmission link and a second transmission link, between the second data device and the first control device. A data driver enables data transmission from the second data device to the first control device across the data link, and a differential controller is adapted to generate a voltage differential between the first transmission link and the second transmission link. A detector detects differences in voltage levels between the first transmission link and the second transmission link. The data communication system enables bi-directional communication between integrated circuit devices over a serial communication link avoiding the necessity for clock, chip enable and control connections on the data device and is particularly useful for communication between an image sensor and coprocessor.

Abstract translation: 数据通信系统包括在第二数据设备和第一控制设备之间的第一控制设备，第二数据设备和包括第一传输链路和第二传输链路的数据链路。 数据驱动器使得能够跨数据链路从第二数据设备到第一控制设备的数据传输，并且差分控制器适于在第一传输链路和第二传输链路之间产生电压差。 检测器检测第一传输链路和第二传输链路之间的电压电平差异。 数据通信系统通过串行通信链路实现集成电路设备之间的双向通信，避免了数据设备上的时钟，芯片使能和控制连接的必要性，并且对于图像传感器和协处理器之间的通信特别有用。

公开(公告)号：US07050436B1

公开(公告)日：2006-05-23

申请号：US09589627

申请日：2000-06-07

Applicant: Howard Gurney

Inventor： Howard Gurney

IPC: H04L12/56

CPC classification number: H04N21/434

Abstract: This invention relates to a device and method for producing a stream of data. The device receives a stream of data as an input and includes means for identifying a portion of the input stream and outputting the identified portion. The device also includes means for selecting a further portion of the input stream and outputting the selected portion. The relative timing between the two output streams is monitored and maintained with respect to the input stream.

Abstract translation: 本发明涉及一种用于产生数据流的装置和方法。 该设备接收数据流作为输入，并且包括用于识别输入流的一部分并输出所识别的部分的装置。 该装置还包括用于选择输入流的另一部分并输出所选部分的装置。 相对于输入流监视和维持两个输出流之间的相对定时。

公开(公告)号：US07017131B2

公开(公告)日：2006-03-21

申请号：US10614336

申请日：2003-07-07

Applicant: Paul Barnes

Inventor： Paul Barnes

IPC: G06F17/50

CPC classification number: G06F17/5068

Abstract: A method of replacing standard cells with high speed cells in the design of a circuit using a computer program, said application specific integrated circuit design comprising a plurality of high speed cells and a plurality of standard cells, said high speed cells and standard cells being arranged to form a plurality of paths on said application specific integrated circuit, said method comprising the steps of: timing said plurality of paths identifying cells occurring on paths for which timing targets are not met; upgrading at least one of said identified cells to a high speed cell.

Abstract translation: 使用计算机程序在电路设计中用高速单元替换标准单元的方法，所述专用集成电路设计包括多个高速单元和多个标准单元，所述高速单元和标准单元被布置 在所述应用专用集成电路上形成多个路径，所述方法包括以下步骤：对所述多个路径进行定时，以识别发生在不满足定时目标的路径上的小区; 将至少一个所述识别的小区升级到高速小区。