Abstract:
A method of designing a clock distribution network in an integrated circuit, the method including: creating a clock distribution network with all cells having a maximum drive strength; supplying parameters of the clock distribution network to a timing analysis tool; in the timing analysis tool, analyzing the timing of the clock distribution network in an iterative process including manipulating the drive strength of at least one cell in the clock distribution network and assessing whether there is an improvement in the timing, wherein the iterative process ceases where there is no improvement in the timing; and outputting a list of cells for which the drive strength was changed.
Abstract:
Nanometer-sized non-superconducting particulates in superconductive REBCO films, where RE is a rare earth metal, for flux pinning enhancement and a method of forming are disclosed. A target with a second phase material sector portion and a superconductive material portion is used in a pulse laser deposition process to form films on substrates according to the present invention. The films consist of 10-20 nm-sized precipitates. In a 0.5 μm thick film, a transport critical current density (Jc)>3 MA/cm2 at 77K in self-field was measured. In one embodiment, magnetization Jc at 77 K and 65K showed significant improvements in a composite YBCO films with fine precipitates produced according to the present invention as compared to non-doped (standard) YBCO films (>10 times increase at 9 T, 65 K).
Abstract:
Scheduling circuitry, for use for example in an ATM network unit to schedule cell transmissions, includes a master calendar (1) for holding entries corresponding respectively to events (cell transmissions) that are to occur within a preselected master-calendar scheduling range (SR), and a slave calendar (12) for holding entries corresponding respectively to events that are to occur beyond that scheduling range. When an event is to be scheduled, calendar control circuitry (24) makes an entry corresponding thereto in the slave calendar (12) if the interval between a current time and a desired scheduling time for the event exceeds said scheduling range. The entry in the slave calendar includes timing information representing the desired scheduling time. The calendar control circuitry monitors the entries in the slave calendar (12) and causes an entry therein whose corresponding event becomes within the scheduling range to be transferred to the master calendar (1). Such scheduling circuitry can deal effectively with events that are to be scheduled at widely disparate intervals (very short and very long) without requiring the calendars to be large and without complicated processing of the calendar entries.
Abstract:
A dispensing apparatus which defines an outlet through which a metered dose of liquid from a reservoir is dispersed as an atomized spray. A droplet of liquid is metered onto a perforate membrane which is vibrated by way of a piezoelectric transducer such that atomized droplets are dispensed through the holes formed in the membrane. At each actuation of a delivery device, which provides the metered quantity of liquid, the transducer is actuated so as to vibrate the membrane for a period greater than the dispensing period required for the droplet to be dispensed. The apparatus is particularly suitable for dispensing pharmaceutical preparations.
Abstract:
A gaming system is arranged to implement a game which is based on credit received. A portion of the credit received is allocated to a credit accumulator. The gaming system is arranged to play one or more feature games for the portion of credit accumulated.
Abstract:
A customer reward system includes at least one activity monitoring device for monitoring trading activity. A processor is associated with the, or each, activity monitoring device for receiving data from said activity monitoring device, for comparing the data with a predetermined trigger condition, the trigger condition being selected from a particular set of conditions, and, when the data and the predetermined trigger condition coincide, generating an output signal indicative of a customer reward.
Abstract:
A method is disclosed for removing impurities from an elastomer intended for medical or pharmaceutical use, which includes a step of performing a first solvent extraction process on the elastomer by contacting the elastomer with a first extracting solvent in a non-supercritical state to substantially remove impurities from the elastomer, thereby leaving a residue of said first extracting solvent in the elastomer. The elastomer is there after subjected to a second solvent extraction process, by contacting the elastomer with a second extracting solvent, which is a supercritical fluid or a mixture of super critical fluids, in order to remove substantially reduce the concentration of the residue of the first extracting solvent remaining in the elastomer after the first solvent extraction process.
Abstract:
A method of cleaning or purifying elastomers and elastomeric articles which are intended for medical or pharmaceutical use is disclosed. In particular, although not exclusively, the invention has applicability to elastomers which are used in metering valves for pressurized metered dose inhalers (MDIs).
Abstract:
A method of designing a clock distribution network in an integrated circuit, the method including: creating a clock distribution network with all cells having a maximum drive strength; supplying parameters of the clock distribution network to a timing analysis tool; in the timing analysis tool, analyzing the timing of the clock distribution network in an iterative process including manipulating the drive strength of at least one cell in the clock distribution network and assessing whether there is an improvement in the timing, wherein the iterative process ceases where there is no improvement in the timing; and outputting a list of cells for which the drive strength was changed.
Abstract:
A method of replacing standard cells with high speed cells in the design of a circuit using a computer program, said application specific integrated circuit design comprising a plurality of high speed cells and a plurality of standard cells, said high speed cells and standard cells being arranged to form a plurality of paths on said application specific integrated circuit, said method comprising the steps of: timing said plurality of paths identifying cells occurring on paths for which timing targets are not met; upgrading at least one of said identified cells to a high speed cell.