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公开(公告)号：US20210367518A1
公开(公告)日：2021-11-25
申请号：US17324782
申请日：2021-05-19
Applicant: STMicroelectronics (Alps) SAS
Inventor： Thomas Jouanneau
Abstract: The integrated circuit includes a first node intended to be biased at a first voltage, a second node intended to be biased at a second voltage and having a non-negligible capacitive coupling with the first node. A power supply management device comprises a voltage booster configured to boost a power supply voltage and comprising boost stages configured to generate intermediate voltages on intermediate nodes. A compatibility detection circuit is configured to detect compatibility between the second voltage and one of the intermediate voltages, and, if the second voltage is compatible with an intermediate voltage, to couple the at least one second node to the compatible intermediate node.
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公开(公告)号：US11114404B2
公开(公告)日：2021-09-07
申请号：US16704082
申请日：2019-12-05
Inventor： Romain Coffy , Patrick Laurent , Laurent Schwartz
Abstract: An integrated circuit chip includes a front face having an electrical connection pad. An overmolded encapsulation block encapsulates the integrated circuit chip and includes a front layer at least partially covering a front face of the integrated circuit chip. A through-hole the encapsulation block is located above the electrical connection pad of the integrated circuit chip. A wall of the through-hole is covered with an inner metal layer that is joined to the front pad of the integrated circuit chip. A front metal layer covers a local zone of the front face of the front layer, with the front metal layer being joined to the inner metal layer to form an electrical connection. The inner metal layer and the front metal layer are attached or anchored to activated additive particles that are included in the material of the encapsulation block.
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公开(公告)号：US20210273548A1
公开(公告)日：2021-09-02
申请号：US17187478
申请日：2021-02-26
Inventor： Alexandre Pons , Jean Camiolo , Meriem Mersel
Abstract: An embodiment of the present disclosure relates to a power supply interface comprising: a converter delivering a first DC voltage; a resistor connected between the converter and an output terminal of the interface delivering a second DC voltage; a first circuit delivering a second signal representative of a difference between the second DC voltage and a voltage threshold when a first signal is in a first state, and at a default value otherwise; a second circuit delivering a third signal representative of a value of a current in first resistor multiplied by a gain of the third circuit, and modifying the gain based on the second signal; and a third circuit configured to deliver a signal for controlling the converter based at least on the third signal.
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公开(公告)号：US20210192304A1
公开(公告)日：2021-06-24
申请号：US17126830
申请日：2020-12-18
Inventor： Julien MERCIER , Pascal NONIER
IPC: G06K19/07
Abstract: A method of managing the power supply of one or more first elements by a second element of a same first device, includes the steps of: sending, to a second device, a time extension request; evaluating during the time extension a power available from an electromagnetic field radiated by the second device; and adjusting the power supply of the second element and of the first element(s) according to the available power.
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215.发明申请公开(公告)号：US20210160134A1
公开(公告)日：2021-05-27
申请号：US16951198
申请日：2020-11-18
Inventor： Nicolas Anquet , Loic Pallardy
IPC: H04L12/24 , H04L12/933
Abstract: System on a chip, comprising several master pieces of equipment, several slave resources, an interconnection circuit capable of routing transactions between master pieces of equipment and slave resources, and a processing unit at least configured to allow a user of the system on a chip to implement within the system on a chip at least one configuration diagram of this system defined by a set of configuration pieces of information including at least one piece of identification information assigned to each master piece of equipment, The identification pieces of information are intended to be attached to all the transactions emitted by the corresponding master pieces of equipment, the set of configuration pieces of information not being used for addressing the slave resources receiving the transactions and being used to define an assignment of at least one piece of master equipment to at least some of the slave resources.
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Patent Agency Ranking
公开(公告)号：US20210135661A1
公开(公告)日：2021-05-06
申请号：US17145863
申请日：2021-01-11
Applicant: STMicroelectronics S.r.l. , STMicroelectronics (Alps) SAS
Abstract: An H-bridge circuit includes a supply voltage node, a first pair of transistors and a second pair of transistors. First transistors in each pair have the current paths therethrough included in current flow lines between the supply node and, respectively, a first output node and a second output node. Second transistors in each pair have the current paths therethrough coupled to a third output node and a fourth output node, respectively. The first and third output nodes are mutually isolated from each other and the second and fourth output nodes are mutually isolated from each other. The H-bridge circuit is operable in a selected one of a first, second and third mode.
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公开(公告)号：US10965212B2
公开(公告)日：2021-03-30
申请号：US16385214
申请日：2019-04-16
Applicant: STMicroelectronics (Alps) SAS
Inventor： Patrik Arno
IPC: H02M3/156
Abstract: In an embodiment, an SMPS comprises a half-bridge, and a driver configured to drive the half-bridge based on a PWM signal. The SMPS further comprising a first circuit coupled between the output of the driver and a control terminal of a high-side transistor of the half-bridge, wherein the first circuit is configured to maintain the first transistor on when the PWM signal has a duty cycle that is substantially 100%.
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公开(公告)号：US10917106B2
公开(公告)日：2021-02-09
申请号：US16709391
申请日：2019-12-10
Applicant: STMicroelectronics SA , STMicroelectronics (Alps) SAS
Inventor： Stephane Le Tual , Jean-Pierre Blanc , David Duperray
Abstract: An acquisition stage receives a digital input signal and generates therefrom a first digital signal and a second digital signal complementary thereto. First and second processing stages receive the first and second digital signals and generate therefrom first and second analog signals in time with first and second complementary clock signals. An output stage generates an internal clock signal equivalent to one of: the first clock signal phase shifted by a duration of a transient occurring during a period of the first clock signal, or the second clock signal phase shifted by a duration of a transient occurring during a period of the second clock signal. The output stage produces an analog output signal equal to the first analog signal when the internal clock signal is at a first logic level, and equal to the second analog signal when the internal clock signal is at a second logic level.
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公开(公告)号：US10670666B2
公开(公告)日：2020-06-02
申请号：US16047743
申请日：2018-07-27
Applicant: STMicroelectronics (Alps) SAS
Inventor： Bruno Leduc , Pascal Bernon , Stephane Clin
IPC: G01R31/40 , G01R19/165 , G01R3/00 , G01R15/14
Abstract: A circuit includes, in series between a first terminal and a second terminal of application of a power supply voltage, and first and second branches. The first branch includes a first transistor and a first current source coupled to the first transistor. The second branch includes a resistive element, a second transistor coupled to the resistive element and forming a current mirror with the first transistor and a second current source coupled to the second transistor. The resistive element conditions a threshold of detection of a variation of the power supply voltage.
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公开(公告)号：US10560020B2
公开(公告)日：2020-02-11
申请号：US16103582
申请日：2018-08-14
Applicant: STMicroelectronics (Alps) SAS
Inventor： Alexandre Pons
Abstract: A method can be used for compensating a voltage drop on a cable connected between a source device and a receiver device. The source device delivers an offset current on a channel configuration pin of the source device, the offset current causing an increase in a voltage on the channel configuration pin of the source device to a chosen reference voltage. The offset current is stored in the source device. The source device absorbs an absorption current originating from the channel configuration pin of the source device, the absorption current depending on the stored offset current and on the voltage drop. The source device generates a compensated supply voltage on a power supply pin of the source device, the compensated supply voltage equal to a reference supply voltage increased by the voltage drop to within a tolerance.
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