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公开(公告)号：US20230327469A1
公开(公告)日：2023-10-12
申请号：US18335690
申请日：2023-06-15
Inventor： Alexandre Pons , Jean Camiolo , Meriem Mersel
IPC: H02J7/00
CPC classification number: H02J7/00712 , H02J7/007192 , H02J2207/20 , H02J2207/30
Abstract: An embodiment of the present disclosure relates to a power supply interface comprising: a converter delivering a first DC voltage; a resistor connected between the converter and an output terminal of the interface delivering a second DC voltage; a first circuit delivering a second signal representative of a difference between the second DC voltage and a voltage threshold when a first signal is in a first state, and at a default value otherwise; a second circuit delivering a third signal representative of a value of a current in first resistor multiplied by a gain of the third circuit, and modifying the gain based on the second signal; and a third circuit configured to deliver a signal for controlling the converter based at least on the third signal.
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公开(公告)号：US11353905B2
公开(公告)日：2022-06-07
申请号：US16787679
申请日：2020-02-11
Inventor： Jean Camiolo , Alexandre Pons
IPC: G05F1/575 , G01R19/165 , G05F3/18 , G06F1/26 , H03F3/45 , H03K3/0233 , G05F1/56
Abstract: A first terminal receives a first DC voltage. A switch selectively couples the first terminal to a second terminal providing an output. A control circuit selectively actuates the switch in response to a comparison of the first DC voltage to a second DC voltage. A low-dropout (LDO) linear voltage regulator, connected between the first and third terminals, operates to provide the second DC voltage from the first DC voltage.
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公开(公告)号：US11710976B2
公开(公告)日：2023-07-25
申请号：US17187478
申请日：2021-02-26
Inventor： Alexandre Pons , Jean Camiolo , Meriem Mersel
CPC classification number: H02J7/00712 , H02J7/007192 , H02J2207/20 , H02J2207/30
Abstract: An embodiment of the present disclosure relates to a power supply interface comprising: a converter delivering a first DC voltage; a resistor connected between the converter and an output terminal of the interface delivering a second DC voltage; a first circuit delivering a second signal representative of a difference between the second DC voltage and a voltage threshold when a first signal is in a first state, and at a default value otherwise; a second circuit delivering a third signal representative of a value of a current in first resistor multiplied by a gain of the third circuit, and modifying the gain based on the second signal; and a third circuit configured to deliver a signal for controlling the converter based at least on the third signal.
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公开(公告)号：US20190235551A1
公开(公告)日：2019-08-01
申请号：US16381541
申请日：2019-04-11
Applicant: STMicroelectronics (Alps) SAS
Inventor： Alexandre Pons
CPC classification number: G05F1/59 , G05F1/56 , G05F1/569 , H01R24/60 , H01R2107/00 , H02J7/022 , H02J7/06 , H02J2007/10 , H03F3/45071 , H03F2203/45521 , H03F2203/45641
Abstract: A low dropout voltage regulator unit includes an error amplifier and a power stage having an output terminal that is looped back onto the error amplifier and is capable of delivering an output current to a load. The unit includes multiple main supply inputs that are intended to potentially receive, respectively, multiple different supply voltages. The power stage includes multiple power paths that are connected, respectively, between the main supply inputs and the output terminal, are individually selectable and each comprise an output transistor. The unit also includes a selector circuit connected to the main supply inputs and configured to select one of the power paths according to a selection criterion. The error amplifier includes an output stage configured to selectively control the output transistor of the selected power path.
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公开(公告)号：US10303192B2
公开(公告)日：2019-05-28
申请号：US15364392
申请日：2016-11-30
Applicant: STMicroelectronics (Alps) SAS
Inventor： Alexandre Pons
IPC: H02J7/00 , G05F1/59 , G05F1/56 , G05F1/569 , H01R24/60 , H02J7/02 , H02J7/06 , H03F3/45 , H01R107/00 , H02J7/10
Abstract: A low dropout voltage regulator unit includes an error amplifier and a power stage having an output terminal that is looped back onto the error amplifier and is capable of delivering an output current to a load. The unit includes multiple main supply inputs that are intended to potentially receive, respectively, multiple different supply voltages. The power stage includes multiple power paths that are connected, respectively, between the main supply inputs and the output terminal, are individually selectable and each comprise an output transistor. The unit also includes a selector circuit connected to the main supply inputs and configured to select one of the power paths according to a selection criterion. The error amplifier includes an output stage configured to selectively control the output transistor of the selected power path.
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Patent Agency Ranking
公开(公告)号：US20190074763A1
公开(公告)日：2019-03-07
申请号：US16103582
申请日：2018-08-14
Applicant: STMicroelectronics (Alps) SAS
Inventor： Alexandre Pons
Abstract: A method can be used for compensating a voltage drop on a cable connected between a source device and a receiver device. The source device delivers an offset current on a channel configuration pin of the source device, the offset current causing an increase in a voltage on the channel configuration pin of the source device to a chosen reference voltage. The offset current is stored in the source device. The source device absorbs an absorption current originating from the channel configuration pin of the source device, the absorption current depending on the stored offset current and on the voltage drop. The source device generates a compensated supply voltage on a power supply pin of the source device, the compensated supply voltage equal to a reference supply voltage increased by the voltage drop to within a tolerance.
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公开(公告)号：US20240126315A1
公开(公告)日：2024-04-18
申请号：US18461950
申请日：2023-09-06
Applicant: STMicroelectronics (Alps) SAS
Inventor： Alexandre Pons
Abstract: The present disclosure relates to a device having a supply input receiving a supply voltage, a switched-mode power supply comprising an output at which is generated a supply voltage, and a voltage linear regulator supplying a load, the regulator receiving the supply voltages, the regulator including two transistors coupled between the supply input, respectively the output of the supply, and an output node of the regulator. When the current drawn by the load is below a threshold, an output current delivered to the load is equal to a current flowing through the transistor, so that, when the current drawn by the load is above the threshold, the output current is equal to a current flowing through the transistor plus a current flowing through the transistor.
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公开(公告)号：US10886844B2
公开(公告)日：2021-01-05
申请号：US16719656
申请日：2019-12-18
Applicant: STMicroelectronics (Alps) SAS
Inventor： Alexandre Pons
Abstract: A controller for compensating a voltage drop on a cable includes an output stage coupled to a channel configuration pin of the source device, a processor coupled to a power supply pin of a source device, and an error amplifier that includes a positive input coupled to a reference voltage, a negative input coupled to the channel configuration pin, a first output coupled to the output stage, and a second output coupled to the processor. The error amplifier is configured to supply a first signal to the output stage indicating a voltage difference between the reference voltage and a voltage at the channel configuration pin. The output stage is configured to supply an output current to the processor using the voltage drop and a stored current determined using the first signal. The processor is configured to generate a compensated supply voltage on the power supply pin using the output current.
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公开(公告)号：US09958889B2
公开(公告)日：2018-05-01
申请号：US14868095
申请日：2015-09-28
Applicant: STMicroelectronics (Alps) SAS
Inventor： Alexandre Pons
CPC classification number: G05F1/575 , H02J1/02 , H02J7/0068 , H02J7/34 , H03K19/0016
Abstract: The present disclosure relates to a voltage regulation circuit including a first transistor connected between an input of voltage to be regulated and an output of a regulated voltage. A first regulation loop controls the first transistor according to a difference between a reference voltage and a first feedback voltage derived from the regulated voltage. A second transistor is connected in series between the first transistor and the output. A second regulation loop controls the second transistor according to a difference between the reference voltage and a second feedback voltage derived from the regulated voltage. The second regulation loop is active in low and high power regulation modes. A switch circuit forces the first transistor into an on state in a low power regulation mode.
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公开(公告)号：US20210273548A1
公开(公告)日：2021-09-02
申请号：US17187478
申请日：2021-02-26
Inventor： Alexandre Pons , Jean Camiolo , Meriem Mersel
Abstract: An embodiment of the present disclosure relates to a power supply interface comprising: a converter delivering a first DC voltage; a resistor connected between the converter and an output terminal of the interface delivering a second DC voltage; a first circuit delivering a second signal representative of a difference between the second DC voltage and a voltage threshold when a first signal is in a first state, and at a default value otherwise; a second circuit delivering a third signal representative of a value of a current in first resistor multiplied by a gain of the third circuit, and modifying the gain based on the second signal; and a third circuit configured to deliver a signal for controlling the converter based at least on the third signal.
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