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公开(公告)号：US11962462B2
公开(公告)日：2024-04-16
申请号：US18321516
申请日：2023-05-22
发明人： Nicolas Anquet , Loic Pallardy
IPC分类号： H04L41/0803 , G06F15/173 , G06F15/177 , H04L41/0813 , H04L49/109 , G06F21/85
CPC分类号： H04L41/0813 , G06F15/17306 , G06F15/177 , H04L41/0803 , H04L49/109 , G06F21/85
摘要： System on a chip, comprising several master pieces of equipment, several slave resources, an interconnection circuit capable of routing transactions between master pieces of equipment and slave resources, and a processing unit at least configured to allow a user of the system on a chip to implement within the system on a chip at least one configuration diagram of this system defined by a set of configuration pieces of information including at least one piece of identification information assigned to each master piece of equipment, The identification pieces of information are intended to be attached to all the transactions emitted by the corresponding master pieces of equipment, the set of configuration pieces of information not being used for addressing the slave resources receiving the transactions and being used to define an assignment of at least one piece of master equipment to at least some of the slave resources.
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公开(公告)号：US20210160193A1
公开(公告)日：2021-05-27
申请号：US17100505
申请日：2020-11-20
申请人： STMicroelectronics (Rousset) SAS , STMicroelectronics (Alps) SAS , STMicroelectronics (Grand Ouest) SAS
发明人： Daniel Olson , Loic Pallardy , Nicolas Anquet
IPC分类号： H04L12/933 , H04L12/24
摘要： System on a chip, comprising several master pieces of equipment, several slave resources, an interconnection circuit coupled between the master pieces of equipment and the slave resources and capable of routing transactions between master pieces of equipment and slave resources. A first particular slave resource cooperates with an element of the system on a chip, for example a clock signal generator, and the element has the same access rights as those of the corresponding first particular slave resource.
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公开(公告)号：US11876732B2
公开(公告)日：2024-01-16
申请号：US17100505
申请日：2020-11-20
申请人： STMicroelectronics (Rousset) SAS , STMicroelectronics (Alps) SAS , STMicroelectronics (Grand Ouest) SAS
发明人： Daniel Olson , Loic Pallardy , Nicolas Anquet
IPC分类号： H04L41/0803 , H04L49/109 , G06F21/85
CPC分类号： H04L49/109 , G06F21/85 , H04L41/0803
摘要： System on a chip, comprising several master pieces of equipment, several slave resources, an interconnection circuit coupled between the master pieces of equipment and the slave resources and capable of routing transactions between master pieces of equipment and slave resources. A first particular slave resource cooperates with an element of the system on a chip, for example a clock signal generator, and the element has the same access rights as those of the corresponding first particular slave resource.
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公开(公告)号：US11700174B2
公开(公告)日：2023-07-11
申请号：US16951198
申请日：2020-11-18
发明人： Nicolas Anquet , Loic Pallardy
IPC分类号： H04L41/0803 , H04L41/0813 , H04L49/109 , G06F15/173 , G06F15/177 , G06F21/85
CPC分类号： H04L41/0813 , G06F15/177 , G06F15/17306 , H04L41/0803 , H04L49/109 , G06F21/85
摘要： System on a chip, comprising several master pieces of equipment, several slave resources, an interconnection circuit capable of routing transactions between master pieces of equipment and slave resources, and a processing unit at least configured to allow a user of the system on a chip to implement within the system on a chip at least one configuration diagram of this system defined by a set of configuration pieces of information including at least one piece of identification information assigned to each master piece of equipment, The identification pieces of information are intended to be attached to all the transactions emitted by the corresponding master pieces of equipment, the set of configuration pieces of information not being used for addressing the slave resources receiving the transactions and being used to define an assignment of at least one piece of master equipment to at least some of the slave resources.
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公开(公告)号：US20210157668A1
公开(公告)日：2021-05-27
申请号：US16953993
申请日：2020-11-20
申请人： STMicroelectronics (Rousset) SAS , STMicroelectronics (Alps) SAS , STMicroelectronics (Grand Ouest) SAS
发明人： Loic Pallardy , Nicolas Anquet , Dragos Davidescu
摘要： In an embodiment a system on chip includes a plurality of microprocessors, a plurality of slave resources, an interconnection circuit coupled between the microprocessors and the slave resources, the interconnection circuit configured to route transactions between the microprocessors and the slave resources and a processing controller configured to allow a user of the system to implement within the system at least one configuration diagram of the system defined by a set of configuration pieces of information used to define an assignment of at least one microprocessor to at least some of the slave resources, select the at least one microprocessors, and authorise an external debugging tool to access, for debugging purposes, only the slave resources assigned to the at least one microprocessor.
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6.发明公开公开(公告)号：US20230291645A1
公开(公告)日：2023-09-14
申请号：US18321516
申请日：2023-05-22
发明人： Nicolas Anquet , Loic Pallardy
IPC分类号： H04L41/0813 , H04L49/109 , G06F15/173 , G06F15/177 , H04L41/0803
CPC分类号： H04L41/0813 , H04L49/109 , G06F15/17306 , G06F15/177 , H04L41/0803 , G06F21/85
摘要： System on a chip, comprising several master pieces of equipment, several slave resources, an interconnection circuit capable of routing transactions between master pieces of equipment and slave resources, and a processing unit at least configured to allow a user of the system on a chip to implement within the system on a chip at least one configuration diagram of this system defined by a set of configuration pieces of information including at least one piece of identification information assigned to each master piece of equipment, The identification pieces of information are intended to be attached to all the transactions emitted by the corresponding master pieces of equipment, the set of configuration pieces of information not being used for addressing the slave resources receiving the transactions and being used to define an assignment of at least one piece of master equipment to at least some of the slave resources.
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公开(公告)号：US20210160134A1
公开(公告)日：2021-05-27
申请号：US16951198
申请日：2020-11-18
发明人： Nicolas Anquet , Loic Pallardy
IPC分类号： H04L12/24 , H04L12/933
摘要： System on a chip, comprising several master pieces of equipment, several slave resources, an interconnection circuit capable of routing transactions between master pieces of equipment and slave resources, and a processing unit at least configured to allow a user of the system on a chip to implement within the system on a chip at least one configuration diagram of this system defined by a set of configuration pieces of information including at least one piece of identification information assigned to each master piece of equipment, The identification pieces of information are intended to be attached to all the transactions emitted by the corresponding master pieces of equipment, the set of configuration pieces of information not being used for addressing the slave resources receiving the transactions and being used to define an assignment of at least one piece of master equipment to at least some of the slave resources.
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公开(公告)号：US11829188B2
公开(公告)日：2023-11-28
申请号：US16953993
申请日：2020-11-20
申请人： STMicroelectronics (Rousset) SAS , STMicroelectronics (Alps) SAS , STMicroelectronics (Grand Ouest) SAS
发明人： Loic Pallardy , Nicolas Anquet , Dragos Davidescu
CPC分类号： G06F11/0751 , G06F11/0721 , G06F11/3656 , G06F13/4282 , G06F21/44 , G06F2213/0016 , G06F2213/0038
摘要： In an embodiment a system on chip includes a plurality of microprocessors, a plurality of slave resources, an interconnection circuit coupled between the microprocessors and the slave resources, the interconnection circuit configured to route transactions between the microprocessors and the slave resources and a processing controller configured to allow a user of the system to implement within the system at least one configuration diagram of the system defined by a set of configuration pieces of information used to define an assignment of at least one microprocessor to at least some of the slave resources, select the at least one microprocessors, and authorise an external debugging tool to access, for debugging purposes, only the slave resources assigned to the at least one microprocessor.
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9.发明公开公开(公告)号：US20240176689A1
公开(公告)日：2024-05-30
申请号：US18514812
申请日：2023-11-20
发明人： Loic Pallardy
IPC分类号： G06F11/07
CPC分类号： G06F11/0772 , G06F11/0745
摘要： The system-on-chip includes at least one master device, at least one slave resource, an interconnection bus including an error notification channel, and a resource isolation system including, for each resource, a protection circuit configured to block or transmit transactions addressed to the resource via the interconnection bus, according to access rights of the resource and the transaction. The protection circuit is capable of generating a notification signal on the error notification channel of the interconnection bus in case of blockage of a transaction.
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公开(公告)号：US20240004804A1
公开(公告)日：2024-01-04
申请号：US18346512
申请日：2023-07-03
发明人： Loic Pallardy , Lionel Debieve
CPC分类号： G06F12/1458 , G06F21/64
摘要： The method for managing access rights of memory regions of a memory comprises assigning an execution permission status for each memory region in a firewall device dedicated to the memory, so that the content of a memory region having an executable status is capable of being executed by a processor, and the content of a memory region having a non-executable status cannot be executed by the processor.
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