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    Memory Array And Method Used In Forming A Memory Array Comprising Strings Of Memory Cells
    212.
    发明申请
    Memory Array And Method Used In Forming A Memory Array Comprising Strings Of Memory Cells 有权

    公开(公告)号：US20220149061A1

    公开(公告)日：2022-05-12

    申请号：US17091420

    申请日：2020-11-06

    Applicant: Micron Technology, Inc.

    Inventor： John D. Hopkins ,  Nancy M. Lomeli

    IPC: H01L27/11556 ,  H01L27/11582 ,  H01L27/1157 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11565

    Abstract: A memory array comprises a conductor tier comprising upper conductor material directly above and directly electrically coupled to lower conductor material. The upper and lower conductor materials comprise different compositions relative one another. Laterally-spaced memory blocks individually comprising a vertical stack comprise alternating insulative tiers and conductive tiers, Channel-material strings of memory cells extend through the insulative tiers and the conductive tiers and through the upper conductor material into the lower conductor material. The channel material of the channel-material strings is directly electrically coupled to the upper and lower conductor materials of the conductor tier. Intervening material is laterally-between and longitudinally-along immediately-laterally-adjacent of the memory blocks. Other embodiments, including method, are disclosed.

    Methods used in forming a memory array comprising strings of memory cells
    214.
    发明授权
    Methods used in forming a memory array comprising strings of memory cells 有权

    公开(公告)号：US11282847B2

    公开(公告)日：2022-03-22

    申请号：US15931116

    申请日：2020-05-13

    Applicant: Micron Technology, Inc.

    Inventor： John D. Hopkins ,  Alyssa N. Scarbrough

    IPC: H01L27/11582 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11565 ,  H01L27/11519 ,  H01L27/11524

    Abstract: A method used in forming a memory array comprising strings of memory cells comprises forming a lower portion of a stack that will comprise vertically-alternating first tiers and second tiers on a substrate. The stack comprises laterally-spaced memory-block regions. Material of the first tiers is of different composition from material of the second tiers. Horizontally-elongated lines are formed in the lower portion that are individually between immediately-laterally-adjacent of the memory-block regions. The lines comprise sacrificial material. The lines individually comprise laterally-opposing projections longitudinally there-along in a lowest of the first tiers. The vertically-alternating first tiers and second tiers of an upper portion of the stack are formed above the lower portion and the lines, and channel-material strings are formed that extend through the first tiers and the second tiers in the upper portion to the lower portion. Horizontally-elongated trenches are formed into the stack that are individually between the immediately-laterally-adjacent memory-block regions and extend to the line there-between. The sacrificial material of the lines and projections is removed through the trenches. Intervening material is formed in the trenches and void-spaces left as a result of the removing of the sacrificial material of the lines. Other embodiments are disclosed.

    METHODS OF FORMING MICROELECTRONIC DEVICES, AND RELATED MICROELECTRONIC DEVICES, MEMORY DEVICES, AND ELECTRONIC SYSTEMS
    215.
    发明申请
    METHODS OF FORMING MICROELECTRONIC DEVICES, AND RELATED MICROELECTRONIC DEVICES, MEMORY DEVICES, AND ELECTRONIC SYSTEMS 有权

    公开(公告)号：US20220077168A1

    公开(公告)日：2022-03-10

    申请号：US17012741

    申请日：2020-09-04

    Applicant: Micron Technology, Inc.

    Inventor： John D. Hopkins ,  Jordan D. Greenlee ,  Nancy M. Lomeli

    IPC: H01L27/11556 ,  H01L27/11582 ,  G11C5/02 ,  G11C5/06 ,  H01L23/538

    Abstract: A method of forming a microelectronic device comprises forming a sacrificial material over a base structure. Portions of the sacrificial material are replaced with an etch-resistant material. A stack structure is formed over the etch-resistant material and remaining portions of the sacrificial material. The stack structure comprises a vertically alternating sequence of insulative material and additional sacrificial material arranged in tiers, and at least one staircase structure horizontally overlapping the etch-resistant material and having steps comprising horizontal ends of the tiers. Slots are formed to vertically extend through the stack structure and the remaining portions of the sacrificial material. The sacrificial material and the additional sacrificial material are selectively replaced with conductive material after forming the slots to respectively form lateral contact structures and conductive structures. Microelectronic devices, memory devices, and electronic systems are also described.

    Integrated Circuitry And Method Used In Forming A Memory Array Comprising Strings Of Memory Cells
    216.
    发明申请
    Integrated Circuitry And Method Used In Forming A Memory Array Comprising Strings Of Memory Cells 有权

    公开(公告)号：US20220068800A1

    公开(公告)日：2022-03-03

    申请号：US17070269

    申请日：2020-10-14

    Applicant: Micron Technology, Inc.

    Inventor： Collin Howder ,  John D. Hopkins ,  Alyssa N. Scarbrough

    IPC: H01L23/522 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11582

    Abstract: A method used in forming a memory array comprising strings of memory cells comprises forming a conductor tier comprising conductor material on a substrate. A lower portion of a stack is formed, with the stack ultimately comprising vertically-alternating first tiers and second tiers above the conductor tier. The stack comprises laterally-spaced memory-block regions. Material of the first tiers is of different composition from material of the second tiers. A lowest of the first tiers comprises conductive first sacrificial material. Conductive second material is directly electrically coupled to the conductive first sacrificial material. The conductive first sacrificial material and the conductive second material have different reduction potentials that are at least 0.5V away from one another. A lowest of the second tiers is insulative and below the lowest first tier. The vertically-alternating first tiers and second tiers of an upper portion of the stack are formed above the lower portion. Channel-material strings are formed that extend through the first tiers and the second tiers in the upper portion to the lowest first tier in the lower portion. Horizontally-elongated trenches are formed into the stack that are individually between immediately-laterally-adjacent of the memory-block regions and extend to the conductive first sacrificial material and the conductive second material in the lowest first tier. The conductive first sacrificial material is galvanically etched through the trenches. The lowest second tier is removed after the galvanically etching. After removing the lowest second tier, conducting material is formed in the lowest first tier that directly electrically couples together the channel material of the individual channel-material strings and the conductor material of the conductor tier. Other embodiments, including structure independent of method, are disclosed.

    Semiconductor constructions
    217.
    发明授权
    Semiconductor constructions 有权

    公开(公告)号：US11251369B2

    公开(公告)日：2022-02-15

    申请号：US15857422

    申请日：2017-12-28

    Applicant: Micron Technology, Inc.

    Inventor： John D. Hopkins

    IPC: H01L45/00 ,  H01L27/24

    Abstract: Some embodiments include constructions having electrically conductive bitlines within a stack of alternating electrically conductive wordline levels and electrically insulative levels. Cavities extend into the electrically conductive wordline levels, and phase change material is within the cavities. Some embodiments include methods of forming memory. An opening is formed through a stack of alternating electrically conductive levels and electrically insulative levels. Cavities are extended into the electrically conductive levels along the opening. Phase change material is formed within the cavities, and incorporated into vertically-stacked memory cells. An electrically conductive interconnect is formed within the opening, and is electrically coupled with a plurality of the vertically-stacked memory cells.

    Memory Arrays Comprising Strings Of Memory Cells And Methods Used In Forming A Memory Array Comprising Strings Of Memory Cells
    219.
    发明申请
    Memory Arrays Comprising Strings Of Memory Cells And Methods Used In Forming A Memory Array Comprising Strings Of Memory Cells 有权

    公开(公告)号：US20210376122A1

    公开(公告)日：2021-12-02

    申请号：US17405151

    申请日：2021-08-18

    Applicant: Micron Technology, Inc.

    Inventor： John D. Hopkins

    IPC: H01L29/66 ,  H01L27/11556 ,  H01L27/11582 ,  H01L27/1157 ,  H01L27/11524

    Abstract: A method used in forming a memory array comprising strings of memory cells comprises forming a conductor tier comprising conductor material on a substrate. A stack is formed comprising vertically-alternating first tiers and second tiers above the conductor tier. The stack comprises laterally-spaced memory-block regions having horizontally-elongated trenches there-between. Channel-material strings extend through the first tiers and the second tiers. Material of the first tiers is of different composition from that of the second tiers. A lowest of the first tiers is thicker than the first tiers there-above. The first-tier material is isotropically etched selectively relative to the second-tier material to form void-space in the first tiers. Conducting material is deposited into the trenches and into the void-space in the first tiers. The conducting material fills the void-space in the first tiers that are above the lowest first tier. The conducting material less-than-fills the void-space in the lowest first tier. The conducting material is etched from the lowest first tier. After the etching of the conducting material, conductive material is deposited into the void-space of the lowest first tier and that directly electrically couples together the channel material of individual of the channel-material strings and the conductor material of the conductor tier. Additional embodiments, including structure independent of method, are disclosed.

    Integrated Assemblies and Methods of Forming Integrated Assemblies
    220.
    发明申请
    Integrated Assemblies and Methods of Forming Integrated Assemblies 有权

    公开(公告)号：US20210358843A1

    公开(公告)日：2021-11-18

    申请号：US16872691

    申请日：2020-05-12

    Applicant: Micron Technology, Inc.

    Inventor： Alyssa N. Scarbrough ,  John D. Hopkins

    IPC: H01L23/522 ,  H01L27/11524 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11582 ,  H01L27/11519 ,  H01L27/11556 ,  H01L23/528 ,  H01L27/11529 ,  H01L27/11573

    Abstract: Some embodiments include a method in which a first stack of alternating first and second levels is formed. At least some of the first and second levels are configured as steps. Each of the steps has one of the second levels and one of the first levels. An etch-stop material and a liner are formed over the stack. A first material is formed over the etch-stop material. Openings are formed to extend through the first material to the etch-stop material. Sacrificial material is formed within the openings. A second stack is formed over the first stack. A second material is formed over the first material. Conductive layers are formed within the first levels. Additional openings are formed to extend to the sacrificial material, and are then extended through the sacrificial material to the conductive layers within the steps. Some embodiments include integrated assemblies.

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