公开(公告)号：US20240349505A1

公开(公告)日：2024-10-17

申请号：US18615110

申请日：2024-03-25

Applicant: Micron Technology, Inc.

Inventor： Yiping Wang ,  Collin Howder

IPC: H10B43/27 ,  H10B41/27

CPC classification number: H10B43/27 ,  H10B41/27

Abstract: Memory circuitry comprising strings of memory cells comprises a stack comprising vertically-alternating insulative tiers and conductive tiers. Channel-material strings of memory cells extend through the insulative tiers and the conductive tiers in a memory-array region. The insulative tiers comprise a first silicon oxide. The insulative tiers and the conductive tiers extend from the memory-array region into a stair-step region. The stair-step region comprises a flight of stairs. The stairs individually comprise a tread comprising conductive material of one of the conductive tiers. Individual of the treads comprise a second silicon oxide directly above the conductive material of the one conductive tier. The second silicon oxide comprises one or more of boron and phosphorus at a total concentration that is greater than a total concentration of one or more of boron and phosphorus, if any, that is in the first silicon oxide that is directly below the second silicon oxide. A conductive-via construction extends downwardly from and directly below the conductive material of the individual treads to circuitry that is directly below the stack. The conductive-via construction comprises conductor material that directly electrically couples together the conductive material of one of the individual treads and the circuitry that is directly below the stack. Methods are disclosed.

公开(公告)号：US12040253B2

公开(公告)日：2024-07-16

申请号：US17508143

申请日：2021-10-22

Applicant: Micron Technology, Inc.

Inventor： Alyssa N. Scarbrough ,  John D. Hopkins ,  Chet E. Carter ,  Justin D. Shepherdson ,  Collin Howder ,  Joshua Wolanyk

IPC: H01L23/48 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35

CPC classification number: H01L23/481 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35

Abstract: A memory array comprising strings of memory cells comprises laterally-spaced memory blocks individually comprising a vertical stack comprising alternating insulative tiers and conductive tiers above a conductor tier. Strings of memory cells comprise channel-material strings that extend through the insulative tiers and the conductive tiers. The channel-material strings directly electrically couple with conductor material of the conductor tier by conducting material that is in a lowest of the conductive tiers and that is directly against multiple of the channel-material strings. A through-array-via (TAV) region comprises TAVs that individually extend through the lowest conductive tier and into the conductor tier. Individual of the TAVs in the lowest conductive tier comprise a conductive core having an annulus circumferentially there-about. The annulus has dopant therein at a total dopant concentration of 0.01 to 30 atomic percent. Insulative material in the lowest conductive tier is circumferentially about the annulus and between immediately-adjacent of the TAVs. Other embodiments, including method, are disclosed.

公开(公告)号：US20240088044A1

公开(公告)日：2024-03-14

申请号：US17940715

申请日：2022-09-08

Applicant: Micron Technology, Inc.

Inventor： Collin Howder ,  Taehyun Kim

IPC: H01L23/535 ,  H01L23/528 ,  H01L27/11556 ,  H01L27/11582

CPC classification number: H01L23/535 ,  H01L23/5283 ,  H01L27/11556 ,  H01L27/11582

Abstract: Methods, systems, and devices for access circuitry structures for three-dimensional (3D) memory arrays are described. A memory device may include levels of memory cells over a substrate. To support accessing memory cells at respective levels, the memory device may include a conductive pillar extending through the levels of memory cells and coupled with one or more memory cells at respective levels of memory cells. The memory device may include a bit line and a contact that is configured to couple the bit line with the conductive pillar. The conductive pillar may be formed such that it extends into a portion of the contact, and a contact resistance between the conductive pillar and the bit line may be based on the conductive pillar extending into the portion of the contact.

公开(公告)号：US20240030285A1

公开(公告)日：2024-01-25

申请号：US17813795

申请日：2022-07-20

Applicant: Micron Technology, Inc.

Inventor： Collin Howder ,  Alyssa N. Scarbrough

IPC: H01L29/08 ,  H01L27/1157 ,  H01L27/11565 ,  H01L29/417

CPC classification number: H01L29/0847 ,  H01L27/1157 ,  H01L27/11565 ,  H01L29/41741 ,  H01L27/11582

Abstract: Electronic devices comprising a source stack comprising one or more conductive materials, a source implant region within a top portion of the source stack, a source contact adjacent to the source stack, sidewalls of the source contact vertically adjacent to the source implant region, a doped semiconductive material adjacent to a source contact, tiers of alternating conductive materials and dielectric materials adjacent to the doped semiconductive material, and pillars extending through the tiers, the doped semiconductive material, and the source contact and into the source stack. Additional electronic devices are also disclosed, as are related methods and electronic systems.

公开(公告)号：US11690226B2

公开(公告)日：2023-06-27

申请号：US17731103

申请日：2022-04-27

Applicant: Micron Technology, Inc.

Inventor： Collin Howder ,  Gordon A. Haller

IPC: H10B43/27 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B43/10 ,  H10B43/35

CPC classification number: H10B43/27 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B43/10 ,  H10B43/35

Abstract: Some embodiments include an integrated structure having a stack of memory cell levels. A pair of channel-material-pillars extend through the stack. A source structure is under the stack. The source structure includes a portion having an upper region, a lower region, and an intermediate region between the upper and lower regions. The upper and lower regions have a same composition and join to one another at edge locations. The intermediate region has a different composition than the upper and lower regions. The edge locations are directly against the channel material of the channel-material-pillars. Some embodiments include methods of forming an integrated assembly.

公开(公告)号：US20220262678A1

公开(公告)日：2022-08-18

申请号：US17736365

申请日：2022-05-04

Applicant: Micron Technology, Inc.

Inventor： Yiping Wang ,  Jordan D. Greenlee ,  Collin Howder

IPC: H01L21/768 ,  H01L23/522 ,  H01L27/11565 ,  H01L27/11519 ,  H01L27/1157 ,  H01L27/11521 ,  H01L27/11556 ,  H01L27/11582

Abstract: A method used in forming a conductive via of integrated circuitry comprises forming a lining laterally over sidewalls of an elevationally-elongated opening. The lining comprises elemental-form silicon. The elemental-form silicon of an uppermost portion of the lining is ion implanted in the elevationally-elongated opening. The ion-implanted elemental-form silicon of the uppermost portion of the lining is etched selectively relative to the elemental-form silicon of a lower portion of the lining below the uppermost portion that was not subjected to said ion implanting. The elemental-form silicon of the lower portion of the lining is reacted with a metal halide to form elemental-form metal in a lower portion of the elevationally-elongated opening that is the metal from the metal halide. Conductive material in the elevationally-elongated opening is formed atop and directly against the elemental-form metal. Other embodiments, including structure independent of method, are disclosed.

公开(公告)号：US20220238684A1

公开(公告)日：2022-07-28

申请号：US17158918

申请日：2021-01-26

Applicant: Micron Technology, Inc.

Inventor： Michael A. Lindemann ,  Collin Howder ,  Yoshiaki Fukuzumi ,  Richard J. Hill

IPC: H01L29/45 ,  H01L27/1157 ,  H01L27/11582 ,  H01L29/792 ,  H01L21/28 ,  H01L29/417

Abstract: Electronic devices comprising a doped dielectric material adjacent to a source contact, tiers of alternating conductive materials and dielectric materials adjacent to the doped dielectric material, and pillars extending through the tiers, the doped dielectric material, and the source contact and into the source stack. Related methods and electronic systems are also disclosed.

公开(公告)号：US11302708B2

公开(公告)日：2022-04-12

申请号：US16674823

申请日：2019-11-05

Applicant: Micron Technology, Inc.

Inventor： Changhan Kim ,  Chet E. Carter ,  Cole Smith ,  Collin Howder ,  Richard J. Hill ,  Jie Li

IPC: H01L27/11582 ,  H01L23/528 ,  H01L27/11568 ,  H01L29/51 ,  H01L29/49 ,  H01L21/311 ,  H01L21/02 ,  H01L27/11521 ,  H01L27/11556 ,  H01L29/788 ,  H01L29/792 ,  H01L29/66 ,  H01L29/10 ,  H01L21/28 ,  H01L27/11529 ,  H01L27/1157

Abstract: Some embodiments include a method of forming an assembly (e.g., a memory array). A first opening is formed through a stack of alternating first and second levels. The first levels contain silicon nitride, and the second levels contain silicon dioxide. Some of the silicon dioxide of the second levels is replaced with memory cell structures. The memory cell structures include charge-storage regions adjacent charge-blocking regions. Tunneling material is formed within the first opening, and channel material is formed adjacent the tunneling material. A second opening is formed through the stack. The second opening extends through remaining portions of the silicon dioxide, and through the silicon nitride. The remaining portions of the silicon dioxide are removed to form cavities. Conductive regions are formed within the cavities. The silicon nitride is removed to form voids between the conductive regions. Some embodiments include memory arrays.

公开(公告)号：US20210287989A1

公开(公告)日：2021-09-16

申请号：US16817267

申请日：2020-03-12

Applicant: Micron Technology, Inc.

Inventor： Jordan D. Greenlee ,  John D. Hopkins ,  Rita J. Klein ,  Everett A. McTeer ,  Lifang Xu ,  Daniel Billingsley ,  Collin Howder

IPC: H01L23/535 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11582 ,  H01L23/522 ,  H01L23/528 ,  H01L23/532 ,  H01L21/768

Abstract: A microelectronic device comprises a stack structure, a staircase structure, conductive pad structures, and conductive contact structures. The stack structure comprises vertically alternating conductive structures and insulating structures arranged in tiers. Each of the tiers individually comprises one of the conductive structures and one of the insulating structures. The staircase structure has steps comprising edges of at least some of the tiers of the stack structure. The conductive pad structures are on the steps of the staircase structure and comprise beta phase tungsten. The conductive contact structures are on the conductive pad structures. Memory devices, electronic systems, and methods of forming microelectronic devices are also described.

公开(公告)号：US11056507B2

公开(公告)日：2021-07-06

申请号：US16927084

申请日：2020-07-13

Applicant: Micron Technology, Inc.

Inventor： Collin Howder ,  Rita J. Klein

IPC: H01L27/11582 ,  G06F3/06 ,  H01L27/1157 ,  H01L27/11556 ,  H01L27/11524

Abstract: A memory array comprises a vertical stack comprising alternating insulative tiers and wordline tiers. The wordline tiers comprise gate regions of individual memory cells. The gate regions individually comprise part of a wordline in individual of the wordline tiers. Channel material extends elevationally through the insulative tiers and the wordline tiers. The individual memory cells comprise a memory structure laterally between the gate region and the channel material. Individual of the wordlines comprise laterally-outer longitudinal-edge portions and a respective laterally-inner portion laterally adjacent individual of the laterally-outer longitudinal-edge portions. The individual laterally-outer longitudinal-edge portions project upwardly and downwardly relative to its laterally-adjacent laterally-inner portion. Methods are disclosed.