公开(公告)号：US10937701B2

公开(公告)日：2021-03-02

申请号：US16038196

申请日：2018-07-18

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Feng-Yi Chang ,  Shih-Fang Tzou ,  Yu-Cheng Tung ,  Ming-Feng Kuo ,  Li-Chiang Chen

IPC: H01L27/108 ,  H01L21/8234

Abstract: A semiconductor device includes a first gate structure in a substrate and a second gate structure in the substrate and adjacent to the first gate structure. Preferably, a top surface of the first gate structure and a top surface of the second gate structure are lower than a top surface of the substrate and a number of work function metal layers in the first gate structure and the second gate structure are different.

公开(公告)号：US10861673B2

公开(公告)日：2020-12-08

申请号：US16143419

申请日：2018-09-26

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chien-Ying Sun ,  En-Chiuan Liou ,  Yu-Cheng Tung

IPC: H01J37/302 ,  H01J37/317 ,  H01L21/027

Abstract: A method of pattern data preparation includes the following steps. A desired pattern to be formed on a surface of a layer is inputted. A first set of beam shots are determined, and a first calculated pattern on the surface is calculated from the first set of beam shots. The first calculated pattern is rotated, so that a boundary of the desired pattern corresponding to a non-smooth boundary of the first calculated pattern is parallel to a boundary constituted by beam shots. A second set of beam shots are determined to revise the non-smooth boundary of the first calculated pattern, thereby calculating a second calculated pattern being close to the desired pattern on the surface. The present invention also provides a method of forming a pattern in a layer.

公开(公告)号：US10777556B2

公开(公告)日：2020-09-15

申请号：US16149125

申请日：2018-10-01

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： En-Chiuan Liou ,  Yu-Cheng Tung

IPC: H01L27/092 ,  H01L21/8238 ,  H01L27/088 ,  H01L21/02 ,  H01L21/8234 ,  H01L21/225 ,  H01L29/66

Abstract: A semiconductor device includes a semiconductor substrate, semiconductor fins; and a first fin bump between the semiconductor fins. The first fin bump includes a first sidewall spacer. The first sidewall spacer includes a solid-state dopant source layer and an insulating buffer layer.

公开(公告)号：US10763175B2

公开(公告)日：2020-09-01

申请号：US16109667

申请日：2018-08-22

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： En-Chiuan Liou ,  Yu-Cheng Tung

IPC: H01L21/82 ,  H01L21/8234 ,  H01L21/308 ,  H01L27/088 ,  H01L29/06 ,  H01L29/78 ,  H01L29/66

Abstract: A semiconductor device and a method of forming the same, the semiconductor device includes a substrate, a plurality of fin shaped structures and an insulating layer. The substrate has a fin field-effect transistor (finFET) region, a first region, a second region and a third region. The first region, the second region and the third region have a first surface, a second surface, and a third surface, respectively, where the first surface is relatively higher than the second surface and the second surface is relatively higher than the third surface. The fin shaped structures are disposed on a surface of the fin field-effect transistor region. The insulating layer covers the first surface, the second surface and the third surface.

公开(公告)号：US20200185511A1

公开(公告)日：2020-06-11

申请号：US16791563

申请日：2020-02-14

Applicant: United Microelectronics Corp

Inventor： EN-CHIUAN LIOU ,  Yu-Cheng Tung

IPC: H01L29/66 ,  H01L21/3115 ,  H01L21/8234 ,  H01L29/78 ,  H01L27/092 ,  H01L21/8238

Abstract: Provided is a semiconductor structure including a substrate, a doping layer, and a dielectric layer. The substrate has a plurality of fin portions and at least one recessed portion, wherein the at least one recessed portion is located between two adjacent fin portions of the plurality of fin portions and a bottom surface of the at least one recessed portion is lower than a surface of the substrate between the two of the plurality of fin portions. The doping layer is disposed on a sidewall of the plurality of fin portions, the surface of the substrate, and a sidewall and a bottom portion of the at least one recessed portion. The dielectric layer is disposed on the doping layer. A top surface of the doping layer and a top surface of the dielectric layer are lower than a top surface of each of the plurality of fin portions.

公开(公告)号：US20200185391A1

公开(公告)日：2020-06-11

申请号：US16789435

申请日：2020-02-13

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Li-Wei Feng ,  Yu-Cheng Tung

IPC: H01L27/108 ,  H01L29/66 ,  H01L27/11573 ,  H01L27/105 ,  H01L29/78 ,  H01L29/51

Abstract: A manufacturing method of a semiconductor memory device includes the following steps. A contact hole is formed on a memory cell region of a semiconductor substrate and exposes a part of the semiconductor substrate. A dielectric layer is formed on the semiconductor substrate. A first trench penetrating the dielectric layer is formed on a memory cell region of the semiconductor substrate. A second trench penetrating the dielectric layer is formed on the peripheral region. A metal conductive layer is formed. The first trench and the second trench are filled with the metal conductive layer for forming a bit line metal structure in the first trench and a first metal gate structure in the second trench. A contact structure is formed in the contact hole, and the contact structure is located between the bit line metal structure and the semiconductor substrate.

公开(公告)号：US10580864B2

公开(公告)日：2020-03-03

申请号：US16022737

申请日：2018-06-29

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yu-Cheng Tung

IPC: H01L29/10 ,  H01L29/78 ,  H01L29/66 ,  H01L21/02 ,  H01L21/308 ,  H01L21/762 ,  H01L27/088 ,  H01L21/8234 ,  H01L29/06 ,  H01L29/165

Abstract: The present invention provides a semiconductor device, including a substrate, a first semiconductor layer, a plurality of first sub recess, a plurality of insulation structures and a first top semiconductor layer. The substrate has a first region disposed within an STI. The first semiconductor layer is disposed in the first region. The first sub recesses are disposed in the first semiconductor layer. The insulation structures are disposed on the first semiconductor layer. The first top semiconductor layer forms a plurality of fin structures, which are embedded in the first sub recesses, arranged alternatively with the insulation structures and protruding over the insulation structures.

公开(公告)号：US10475932B2

公开(公告)日：2019-11-12

申请号：US15828060

申请日：2017-11-30

Applicant: United Microelectronics Corp.

Inventor： Shao-Hui Wu ,  Yu-Cheng Tung

IPC: H01L29/786 ,  H01L29/10 ,  H01L29/78 ,  H01L27/092 ,  H01L21/8238 ,  H01L29/66 ,  H01L21/8258

Abstract: A transistor structure includes a first oxide semiconductor layer, a source structure and a drain structure, and a second oxide semiconductor layer. The first oxide semiconductor layer is doped with sulfur. The source structure and the drain structure are disposed on the first oxide semiconductor layer, and a region of the first oxide semiconductor layer between the source structure and the drain structure forms a channel region. The second oxide semiconductor layer doped with sulfur is at least formed on the channel region of the first oxide semiconductor layer.

公开(公告)号：US10460997B2

公开(公告)日：2019-10-29

申请号：US16360019

申请日：2019-03-21

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： En-Chiuan Liou ,  Yu-Cheng Tung ,  Chih-Wei Yang

IPC: H01L27/14 ,  H01L21/8234 ,  H01L29/06 ,  H01L27/12 ,  H01L21/84 ,  H01L27/088 ,  H01L29/08 ,  H01L21/82 ,  H01L29/66

Abstract: A semiconductor device includes a semiconductor substrate, an isolation structure, and a spacer. The semiconductor substrate includes at least one fin structure. The isolation structure is partly disposed in the fin structure and partly disposed above the fin structure. The fin structure includes a first fin and a second fin elongated in the same direction. A part of the isolation structure is disposed between the first fin and the second fin in the direction where the first fin and the second fin are elongated. The spacer is disposed on sidewalls of the isolation structure on the fin structure. The isolation structure in the present invention is partly disposed in the fin structure and partly disposed above the fin structure. The negative influence of a gate structure formed on the isolation structure and sinking into the isolation structure on the isolation performance of the isolation structure may be avoided accordingly.

公开(公告)号：US10431679B2

公开(公告)日：2019-10-01

申请号：US15942568

申请日：2018-04-01

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Feng-Yi Chang ,  Yu-Cheng Tung ,  Fu-Che Lee

IPC: H01L29/00 ,  H01L29/78 ,  H01L21/4757 ,  H01L21/02 ,  H01L21/762 ,  H01L27/108 ,  H01L29/66 ,  H01L29/423

Abstract: A semiconductor structure and a method for forming the same are provided. The semiconductor structure includes a substrate and at least a gate trench extending along a first direction formed in the substrate. A gate dielectric layer is formed conformally covering the gate trench. A gate metal is formed on the gate dielectric layer and filling the gate trench. A plurality of intervening structures are arranged along the first direction in a lower portion of the gate trench and disposed between the gate metal and the gate dielectric layer.