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公开(公告)号：US20240210816A1
公开(公告)日：2024-06-27
申请号：US18165937
申请日：2023-02-08
发明人： Chia-Chen Sun , En-Chiuan Liou , Song-Yi Lin
IPC分类号： G03F1/70 , G03F1/36 , G06F30/392
CPC分类号： G03F1/70 , G03F1/36 , G06F30/392
摘要： A method includes providing a layout pattern to a computer system. The layout pattern includes a first pattern, a second pattern, and a third pattern. A central line defined by connecting a line end of the second pattern and a line end of the third pattern overlaps with a middle portion of the first pattern. An optical proximity correction (OPC) is performed on the layout pattern to form a first auxiliary pattern. The first auxiliary pattern includes a first stripe pattern and a second stripe pattern both extending from the line end of the second pattern. The second stripe pattern is closer to the first pattern than the first stripe pattern, and an extending length of the second stripe pattern is less than an extending length of the first stripe pattern. The layout pattern and the first auxiliary pattern are outputted through the computer system onto a photomask.
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公开(公告)号：US20240085780A1
公开(公告)日：2024-03-14
申请号：US17965730
申请日：2022-10-13
发明人： Chia-Chen Sun , En-Chiuan Liou , Song-Yi Lin
摘要： A photomask structure having a first region and a second region is provided. The layout pattern density of the first region is smaller than the layout pattern density of the second region. The photomask structure includes a first layout pattern, a second layout pattern, and first assist patterns. The first layout pattern is located in the first region and the second region. The second layout pattern is located in the second region. The second layout pattern is located on one side of the first layout pattern. The first assist patterns are located on the first sidewall of the first layout pattern and separated from each other. The first sidewall is adjacent to the second layout pattern. The first assist patterns are adjacent to a boundary between the first region and the second region. The lengths of two adjacent first assist patterns decrease in the direction away from the boundary.
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公开(公告)号：US20230411308A1
公开(公告)日：2023-12-21
申请号：US17864407
申请日：2022-07-14
发明人： Chia-Chen Sun , En-Chiuan Liou
IPC分类号： H01L23/00 , H01L23/522 , H01L23/528
CPC分类号： H01L23/562 , H01L23/5226 , H01L23/528
摘要： Provided is a semiconductor structure including a first and a second conductive layers, and a first group of vias. The second conductive layer is disposed on the first conductive layer. The first group of vias is disposed between and connects the first and the second conductive layer. The first group of vias includes a first, a second, a third and a fourth vias. The first and second vias are arranged in a first column. The third and fourth vias are arranged in a second column. The first via is adjacent to the third via. The second via is adjacent to the fourth via. The extension directions of the first and second vias are orthogonal to each other, the extension directions of the third and the fourth vias are orthogonal to each other, and the extending directions of the first and the third vias are orthogonal to each other.
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公开(公告)号：US20230260930A1
公开(公告)日：2023-08-17
申请号：US17691130
申请日：2022-03-10
发明人： Chia-Chen Sun , En-Chiuan Liou
CPC分类号： H01L23/562 , H01L23/585
摘要： A die seal ring structure includes a metal interconnect structure on a substrate, in which the metal interconnect structure includes an inter-metal dielectric (IMD) layer on the substrate and a first metal interconnection disposed in the IMD layer. Preferably, a first side of the first metal interconnection includes a comb-shape portion in a top view, a second side of the first metal interconnection includes a linear line, a third side of the first metal interconnection includes a linear line, and a fourth side of the first metal interconnection includes a linear line.
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公开(公告)号：US10763264B2
公开(公告)日：2020-09-01
申请号：US16571202
申请日：2019-09-16
发明人： En-Chiuan Liou , Yu-Cheng Tung , Chih-Wei Yang , Sho-Shen Lee
IPC分类号： H01L27/108 , G11C11/401
摘要： The present invention provides a method for forming a dynamic random access memory (DRAM) structure, the method including: firstly, a substrate is provided, a cell region and a peripheral region are defined on the substrate, a plurality of buried word lines is then formed in the cell region of the substrate, next, a shallow trench isolation structure is formed in the peripheral region adjacent to the cell region, wherein a concave top surface is formed on the shallow trench isolation structure, afterwards, a first dummy bit line gate is formed within the shallow trench isolation structure of the peripheral area, and a second dummy bit line gate is formed in the cell region and adjacent to the first dummy bit line gate, wherein a top surface of the first dummy bit line gate is lower than a top surface of the second dummy bit line gate.
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公开(公告)号：US20200111791A1
公开(公告)日：2020-04-09
申请号：US16178521
申请日：2018-11-01
发明人： Chia-Hung Wang , En-Chiuan Liou , Chien-Hao Chen , Sho-Shen Lee , Yi-Ting Chen , Jhao-Hao Lee
IPC分类号： H01L27/108 , H01L21/033 , H01L21/027 , H01L21/311
摘要： A method of forming a layout of a semiconductor device includes the following steps. First line patterns extend along a first direction in a first area and a second area, but the first line patterns extend along a second direction in a boundary area. Second line patterns extend along a third direction in the first area and the second area, but the second line patterns extend along a fourth direction in the boundary area, so that minimum distances between overlapping areas of the first line patterns and the second line patterns in the boundary area are larger than minimum distances between overlapping areas of the first line patterns and the second line patterns in the first area and the second area. A trimming process is performed to shade the first line patterns and the second line patterns in the boundary area and the second area.
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公开(公告)号：US20200013724A1
公开(公告)日：2020-01-09
申请号：US16049826
申请日：2018-07-31
发明人： Zheng-Feng Chen , Sho-Shen Lee , En-Chiuan Liou , Hsiao-Lin Hsu , Yi-Ting Chen , Lu-Wei Kuo
IPC分类号： H01L23/544 , H01L27/108 , H01L21/027 , H01L21/311 , H01L21/3213
摘要： A method of forming an overlay mark structure includes the following steps. An insulation layer is formed on a substrate. A first overlay mark is formed in the insulation layer. A metal layer is formed on the substrate. The metal layer covers the insulation layer and the first overlay mark. The metal layer on the first overlay mark is removed. A top surface of the first overlay mark is lower than a top surface of the insulation layer after the step of removing the metal layer on the first overlay mark. A second overlay mark is formed on the metal layer. In the method of forming the overlay mark structure, the first overlay mark may not be covered by the metal layer for avoiding influences on related measurements, and the second overlay mark may be formed on the metal layer for avoiding related defects generated by the height difference.
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公开(公告)号：US20190393099A1
公开(公告)日：2019-12-26
申请号：US16562454
申请日：2019-09-06
发明人： En-Chiuan Liou , Yu-Cheng Tung , Chih-Wei Yang
IPC分类号： H01L21/8234 , H01L29/08 , H01L29/06 , H01L27/088 , H01L27/12 , H01L21/84
摘要： A semiconductor device includes a semiconductor substrate, a gate structure, an isolation structure, and a source/drain region. The semiconductor substrate includes a fin. The gate structure is disposed on the fin and is disposed straddling the fin. The isolation structure covers a sidewall and a top surface of the fin. The source/drain region is disposed in the fin and extends beyond the top surface of the fin.
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公开(公告)号：US20190273083A1
公开(公告)日：2019-09-05
申请号：US15936396
申请日：2018-03-26
发明人： En-Chiuan Liou , Yu-Cheng Tung , Chih-Wei Yang , Sho-Shen Lee
IPC分类号： H01L27/108 , G11C11/401
摘要： The present invention provides a dynamic random access memory structure, comprising a substrate defining a cell region and a peripheral region on the substrate, a shallow trench isolation structure located in the peripheral region adjacent to the cell region, wherein the shallow trench isolation structure has a concave top surface, a first dummy bit line gate located within the shallow trench isolation structure of the peripheral area, and a second dummy bit line gate located in the cell region and adjacent to the first dummy bit line gate, wherein a top surface of the first dummy bit line gate is lower than a top surface of the second dummy bit line gate.
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公开(公告)号：US20190267373A1
公开(公告)日：2019-08-29
申请号：US16407188
申请日：2019-05-09
发明人： En-Chiuan Liou , Yu-Cheng Tung , Chih-Wei Yang
IPC分类号： H01L27/088 , H01L29/78 , H01L29/66 , H01L21/762 , H01L21/8234
摘要： A manufacturing method of a semiconductor device includes the following steps. A semiconductor substrate including at least one fin structure is provided. A gate material layer is formed on the semiconductor substrate, and the fin structure is covered by the gate material layer. A trench is formed partly in the gate material layer and partly in the fin structure. An isolation structure is formed partly in the trench and partly outside the trench. At least one gate structure is formed straddling the fin structure by patterning the gate material layer after the step of forming the isolation structure. A top surface of the isolation structure is higher than a top surface of the gate structure in a vertical direction for enhancing the isolation performance of the isolation structure. A sidewall spacer is formed on sidewalls of the isolation structure, and there is no gate structure formed on the isolation structure.
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